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users manual 10.94 data communications ics high-level serial communication controller extended (hscx) sab 82525; sab 82526 saf 82525; saf 82526
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irrevers- ible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about processing guidelines and quality assurance for ics, see our product overview . sab 82525; saf 82525; sab 82526; saf 82526 revision history: 10.94 previous releases: 01.92 page subjects (changes since last revision) update published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, d-81541 mnchen siemens ag 1994. all rights reserved. as far as patents or other rights of third parties are concerned, liability is only assumed for components , not fo r applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery, and prices please contact the offices of semiconductor group in german y or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the type in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. edition 10.94 this edition was realized using the software system framemaker .
general information semiconductor group 3 table of contents page 1features ..................................................................................................................... 6 1.1 pin definitions and functions ................................................................................... 10 1.2 system integration .................................................................................................... 17 1.3 functional description .............................................................................................. 22 2 operating modes ..................................................................................................... 24 2.1 auto-mode (mode: mds1, mds0 = 00) .................................................................. 24 2.2 non-auto mode (mode: mds1, mds0 = 01) .......................................................... 24 2.3 transparent mode 1 (mode: mds1, mds0, adm = 101) ....................................... 25 2.4 transparent mode 0 (mode: mds1, mds0, adm = 100) ....................................... 25 2.5 extended transparent modes 0; 1 (mode: mds1, mds0 = 11) ............................. 25 2.6 receive data flow (summary) ................................................................................. 26 2.7 transmit data flow ................................................................................................... 27 3 procedural support (layer-2 functions) .............................................................. 28 3.1 full-duplex lapb/lapd operation .......................................................................... 28 3.2 half-duplex sdlc-nrm operation .......................................................................... 34 3.3 error handling ........................................................................................................... 38 4 cpu interface .......................................................................................................... 38 4.1 register set .............................................................................................................. 3 8 4.2 data transfer modes ................................................................................................. 38 4.3 interrupt interface ...................................................................................................... 39 4.4 dma interface ........................................................................................................... 43 4.5 fifo structure .......................................................................................................... 47 5 serial interface (layer-1 functions) ...................................................................... 49 5.1 clock modes .............................................................................................................. 49 5.2 clock recovery (dpll) ............................................................................................ 57 5.3 bus configuration ..................................................................................................... 60 5.4 data encoding .......................................................................................................... 63 5.5 modem control functions (rts/cts, cd) ............................................................... 63 6 special functions ................................................................................................... 65 6.1 fully transparent transmission and reception ....................................................... 65 6.2 cyclic transmission (fully transparent) ................................................................... 65 6.3 continuous transmission (dma mode only) ............................................................ 66 6.4 receive length check feature ................................................................................ 66 6.5 one bit insertion ....................................................................................................... 67 6.6 data inversion........................................................................................................... 67
general information semiconductor group 4 table of contents page 6.8 test mode ................................................................................................................. 6 8 6.7 special rts function ............................................................................................... 68 7 operational description ......................................................................................... 69 7.1 reset ...................................................................................................................... 69 7.2 initialization ............................................................................................................. .. 70 7.3 operational phase .................................................................................................... 71 7.4 data transmission .................................................................................................... 71 7.5 data reception ......................................................................................................... 75 8 detailed register description ................................................................................ 79 8.1 register address arrangement ................................................................................. 79 8.2 register definitions ................................................................................................... 80 9 electrical characteristics ..................................................................................... 108 10 quartz specifications ........................................................................................... 118 11 package outlines .................................................................................................. 125
general information semiconductor group 5 advanced cmos technology low power consumption: active 25 mw at 4 mhz standby 4 mw general the sab 82525 is a high-level serial communication controller compatible to the sab 82520 hscc with extended features and functionality (hscx). the sab 82526 is pin and software compatible to the sab 82525, realizing one hdlc channel (channel b). the hscx has been designed to implement high-speed communication links using hdlc protocols and to reduce the hardware and software overhead needed for serial synchronous communications. due to its 8-bit demultiplexed adaptive bus interface it fits perfectly into every siemens/intel or motorola 8- or 16-bit microcontroller or microprocessor system. the data through-put from/to system memory is optimized transferring blocks of data (usually 32 bytes) by means of dma or interrupt request. together with the storing capacity of up to 64 bytes in on-chip fifos, the serial interfaces are effectively decoupled from the system bus which drastically reduces the dynamic load and reaction time of the cpu. the hscx directly supports the x.25 lapb, the isdn lapd, and sdlc (normal response mode) protocols and is capable of handling a large set of layer-2 protocol functions independently from the host processor. furthermore, the hscx opens a wide area for applications which use time division multiplex methods (e.g. time-slot oriented pcm systems, systems designed for packet switching, isdn applications) by its programmable telecom-specific features. the hscx is fabricated using siemens advanced acmos 3 technology and available in a p-lcc-44 pin package. the data link controller handles all functions necessary to establish and maintain an hdlc data link, such as C flag insertion and detection, C bit stuffing, C crc generation and checking, C address field recognition. associated with each serial channel is a set of independent command and status registers (sp-reg) and 64-byte deep fifos for transmit and receive direction. dma capability has been added to the hscx by means of a 4-channel dma interface (sab 82525) with one dma request line for each transmitter and receiver of both channels.
semiconductor group 6 82525 82526 82525 82526 sab sab saf saf type ordering code package sab 82525 n q67100-h6486 p-lcc-44-1 (smd ) sab 82526 n q67100-h6512 p-lcc-44-1 (smd) saf 82525 n q67100-h6504 p-lcc-44-1 (smd) saf 82526 n q67100-h6511 p-lcc-44-1 (smd) sab 82525 h q67101-h6482 p-mqfp-44-2 (smd) 1features preliminary data cmos ic two independent full-duplex hdlc channels (sab 82526: one channel) serial interface different modes of data encoding modem control lines (rts, cts, cd) support of bus configuration by collision resolution programmable bit inversion transparent receive/transmit of data bytes without hdlc framing continuous transmission of 1 to 32 bytes possible data rate up to 4 mbit/s on chip clock generation or external clock source on chip dpll for clock recovery for each channel C C C C two independent baudrate generators (sab 82526: one baudrate generator) independent time-slot assignment for each channel with programmable time-slot length (1-256 bit) high-level serial communications controller extended (hscx) 82525 82526 82525 82526 sab sab saf saf 10.94 p-lcc-44-1 p-mqfp-44-2
semiconductor group 7 82525 82526 82525 82526 sab sab saf saf features (contd) protocol support C C C auto-mode non-auto mode transparent mode various types of protocol support depending on operating mode handling of bit oriented functions in all modes support of lapb/lapd/sdlc/hdlc protocol in auto-mode ( i - and s-frame handling) modulo 8 or modulo 128 operation programmable time-out and retry conditions programmable maximum packet size checking 64 byte fifos per channel and direction storage capacity of up to 17 short frames in receive direction efficient transfer of data blocks from/to system memory by dma or interrupt request 8-bit demultiplexed or multiplexed bus interface intel or motorola type m p interface m p interface
semiconductor grou p 8 82525 82526 82525 82526 sab sab saf saf pin configurations (top view) 18 19 20 21 22 23 24 25 26 27 28 im1 ale/im0 v a6 a5 a4 a3 a2 a1 a0 int 29 dackb 30 dacka 31 axclkb 32 txclkb 33 rxclkb 34 axclka 35 rxclka 36 txclka 37 drqrb 38 drqtb 39 drqra 7 8 9 10 11 12 13 14 15 16 17 40 41 42 43 44 1 2 3 4 5 6 res rxdb rtsb ctsb/cxdb txdb txda ctsa/cxda rtsa rxda cs wr/ic0 rd/ic1 d7 d6 d5 d4 d3 d2 d1 d0 drqta v dd itp00944 ss hscx sab 82525 saf 85525 p-lcc-44 18 19 20 21 22 23 24 25 26 27 28 im1 ale/im0 v a6 a5 a4 a3 a2 a1 a0 int 29 dackb 30 n.c. 31 axclkb 32 txclkb 33 rxclkb 34 axclka 35 rxclka 36 n.c. 37 drqrb 38 drqtb 39 n.c. 7 8 9 10 11 12 13 14 15 16 17 40 41 42 43 44 1 2 3 4 5 6 res rxdb rtsb ctsb/cxdb txdb n.c. n.c. n.c. n.c. cs wr/ic0 rd/ic1 d7 d6 d5 d4 d3 d2 d1 d0 n.c. v dd itp00945 ss hscx sab 82526 saf 82526 p-lcc-44 1
semiconductor group 9 82525 82526 82525 82526 sab sab saf saf pin configurations (top view) 22 int v dd 0 d im ss v 0 cs rxda rtsa ctsa/cxda txdb ctsb/cxdb rtsb rxdb res 12 13 14 15 16 17 18 19 20 21 itp05885 44 23 11 43 42 41 40 39 38 37 36 35 34 10 24 925 826 727 628 529 430 331 232 133 drqra drqtb drqrb txclka axclka axclkb dacka dackb rxclka rxclkb drqta d1 d2 d3 d4 d5 d6 d7 1 rd/ic ale/im a0 0 1 1 a 2 a 3 a 4 a 5 a 6 a txclkb txda wr/ic hscx sab 82525 h p-mqfp-44-2
semiconductor group 10 82525 82526 82525 82526 sab sab saf saf 1.1 pin definitions and functions pin no. symbol input ( i ) output (o) function 6 rd /ic1 i 7 wr /ic0 i write , intel bus mode this signal indicates a write operation. when cs is active the hscx loads an internal register with data provided via the data bus. when dack is active for dma transfers the hscx loads data from the data bus on the top of the respective transmit fifo. input control motorola bus mode in motorola bus mode, this pin serves as the r/w input to distinguish between read or write operations. 42 43 44 1 2 3 4 5 d0 d1 d2 d3 d4 d5 d6 d7 i /o data bus the data bus lines are bidirectional threestate lines which interface with the systems data bus. these lines carry data and command/status to and from the hscx. 8 cs i chip select a low signal selects the hscx for a read/write operation. input control 1 , motorola bus mode im1 connected to high. if motorola bus mode has been selected this pin serves either as e = enable, active high (im0 tied to low) or ds = data strobe, active low (im0 tied to high) input (depending on the selection via im0) to control read/ write operations. read , intel bus mode, im1 connected to low this signal indicates a read operation. when the hscx is selected via cs the read signal enables the bus drivers to put data from an internal register addressed via a0-a6 on the data bus. when the hscx is selected for dma transfers via dack, the rd signal enables the bus driver to put data from the respective receive fifo on the data bus. inputs to a0-a6 are ignored. p-lcc p-mqfp 11 12 3 4 5 6 7 8 9 10 13
semiconductor group 11 82525 82526 82525 82526 sab sab saf saf pin definitions and functions (contd) pin no. symbol input ( i ) output (o) function 9 16 rxda rxdb i receive data (channel a/channel b) serial data is received on these pins at standard ttl or cmos levels. 10 15 o 11 14 i clear to send (channel a/channel b) a low on the cts inputs enables the respective transmitter. additionally, an interrupt may be issued if a state transition occurs at the cts pin (programmable feature). if no "clear to send" function is required, the cts inputs can be connected directly to v ss . collision data (channel a/channel b) in a bus configuration, the external serial bus must be connected to the respective c d pin for collision detection. 12 13 txda txdb o transmit data (channel a/channel b) transmit data is shifted out via these pins at standard ttl or cmos levels. these pins can be programmed to work either as push-pull, or open drain outputs supporting bus configurations. 17 res i reset a high signal on this input forces the hscx into the reset state. the hscx is in power-up mode during reset and in power-down mode after reset. the minimum pulse width is 1.8 m s. request to send (channel a/channel b) when the rts bit in the mode register is set, the rts signal goes low. when the rts is reset, the signal goes high if the transmitter has finished and there is no further request for a transmission. in a bus configuration, this pin can be programmed via ccr2 to: stay always high (rts disabled). go low during the actual transmission of a frame shifted by one clock period, excluding collision bits go low during the reception of a data frame C C C rtsa rtsb ctsa / cxda ctsb / cxdb 14 21 15 20 16 19 17 18 22 p-lcc p-mqfp
semiconductor group 12 82525 82526 82525 82526 sab sab saf saf pin definitions and functions (contd) pin no. symbol input ( i) output (o) function 18 im1 i input mode 1 connecting this pin to either v ss or v dd the bus interface can be adapted to either siemens/intel or motorola environment. im1 = low: intel bus mode im1 = high: motorola bus mode 19 ale/ im0 i address latch enable (intel bus mode) a high on this line indicates an address on the external address/data bus, which will select one of the hscxs internal registers. the address is latched by the hscx with the falling edge of ale. this allows the hscx to be directly connected to a cpu with multiplexed address/data bus compatible to sab 82520 hscc. the address input pins a0-a6 must be externally connected to the data bus pins (d0-d6 for 8-bit cpus, d1- d7 for 16-bit cpus, i.e. multiply all internal register addresses by 2). this pin should be connected to high for a de-multiplexed bus. input mode 0 , motorola bus mode in motorola bus mode, the level at this pin determines the function of the ic1 pin (see description of pin 6). 20 v ss i ground 27 26 25 24 23 22 21 a0 a1 a2 a3 a4 a5 a6 i address bus these inputs interface with seven bits of the systems address bus to select one of the internal registers for read or write. they are usually connected at a0-a6 in 8-bit systems or at a1-a7 in 16-bit systems. 23 24 25 32 31 30 29 28 27 26 p-lcc p-mqfp
semiconductor group 13 82525 82526 82525 82526 sab sab saf saf int pin definitions and functions (contd) pin no. symbol input (i) output (o) function 30 29 i 34 31 axclk a axclk b i dma acknowledge (channel a/channel b) when low, this input signal from the dma controller notifies, the hscx, that the requested dma cycle controlled via drqxx (pins 37C40) is in progress, i.e. the dma controller has achieved bus mastership from the cpu and will start data transfer cycles (either read or write). together with rd , if dma has been requested from the receiver, or with wr , if dma has been requested from the transmitter, this input works like cs to enable a data byte to be read from or written to the top of the receive or transmit fifo of the specified channel. if dackn is active, the input on pins a0Ca6 is ignored and the fifos are implicitly selected. if the dackn signals are not used, these pins must be connected to v dd . alternative clock (channel a/channel b) these pins realize several input functions. depending on the selected clock mode, they may supply either a this pin can be programmed to functions as receiver enable if the "auto start" feature is selected (cas bit in xbch set). the state at this pin can be read from vstr register, or a receive strobe signal (clock mode 1) C or a frame synchronization signal in time-slot oriented operation mode (clock mode 5) C or, together with rxclk, a crystal connection for the internal oscillator (clock mode 4, 6, 7, axclk a only). C cd (= carrier detect) modem control or general purpose input. C dacka dackb 28 od interrupt request the signal is activated, when the hscx requests an interrupt. the cpu may determine the particular source and cause of the interrupt by reading the hscxs interrupt status registers. (ista, exir). int is an open drain output, thus the interrupt requests outputs of several hscxs can be connected to one interrupt input in a "wired-or" combination. this pin must be connected to a pull-up resistor. p-lcc p-mqfp 35 34 39 36 33
semiconductor group 14 82525 82526 82525 82526 sab sab saf saf pin definitions and functions (contd) pin no. symbol input ( i ) output (o) function 36 32 txclk a txclk b i/ o 35 33 rxclk a rxclk b i 39 37 drqra drqrb o transmit clock (channel a/channel b) the functions of these pins depend on the programmed clock mode, provided that the tss bit in the ccr2 register is reset. programmed as inputs (if the tio bit in ccr2 is reset), they may supply either the transmit clock for the respective channel (clock mode 0, 2, 6), C or a transmit strobe signal (clock mode 1). C programmed as outputs (if the tio bit in ccr2 is set), the txclk pins supply either the transmit clock of the respective channel which is generated either C from the baudrate generator (clock mode 2, 6; tss bit in ccr2 set), or from the dpll circuit (clock mode 3, 7), or from the crystal oscillator (clock mode 4) or a tristate control signal indicating the programmed transmit time-slot (clock mode 5). C receive clock (channel a/channel b) the functions of these pins also depend on the programmed clock mode. in each channel, rxclk may supply either or a crystal connection for the internal oscillator (clock mode 4,6,7, rxclk a/b together with axclk a) C or the clock for the baudrate generator (clock mode 2, 3), C or the receive and transmit clock (clock mode 1, 5) C the receive clock (clock mode 0) C dma request receiver (channel a/channel b) the receiver of the hscx requests a dma data transfer by activating this line. the drqrn remains high as long as the receive fifo requires data transfers, thus always blocks of data (32, 16, 8 or 4 bytes) are transferred. drqrn is deactivated immediately following the falling edge of the last read cycle. 41 37 40 38 44 42 p-lcc p-mqfp
semiconductor group 15 82525 82526 82525 82526 sab sab saf saf pin definitions and functions (contd) pin no. symbol input ( i) output (o) function 40 38 drqta drqtb o dma request transmitter (channel a/channel b) the transmitter of the hscx requests a dma data transfer by activating this line. the drqtn remains high as long as the transmit fifo requires data transfers. the amount of data bytes to be transferred from system memory to the hscx (= byte count) must be written first to the xbch, xbcl registers. always blocks of data (n x 32 bytes + rest, n = 0, 1,) are transferred till the byte count is reached. drqtn is deactivated immediately following the falling edge of the last wr cycle. 41 v dd i power supply + 5 v. 1 43 2 p-lcc p-mqfp
semiconductor group 16 82525 82526 82525 82526 sab sab saf saf figure 1 block diagram sab 82525/sab 82526 the hscx sab 82526 comprises one (channel b), the sab 82525 two completely independent full-duplex hdlc channels (channel a and channel b), supporting various layer-1 functions by means of internal oscillator, baud rate generator (brg), digital phase locked loop (dpll), and time-slot assignment (tsa) circuits. furthermore, layer-2 functions are performed by an on-chip lap (link access procedure, e.g. lapb or lapd) controller. p bus interface sp-reg lap controller fifo transmit receive fifo data link controller tsa decoder collision detection dpll clock controll dma interface channel a itb00946 channel b a0-a6 d0-d7 rd/ic1 wr/ic0 cs ale/imo int res im1 drqta drqra dacka dackb drqrb drqtb brg rxda txda rtsa ctsa/ cxda txclkb axclkb rxclkb txdb rtsb cxdb rxdb ctsb/ txclka axclka rxclka
semiconductor group 17 82525 82526 82525 82526 sab sab saf saf 1.2 system integration general aspects figure 2 gives a general overview of the system integration of hscx. figure 2 general system integration of hscx the hscx bus interface consists of an 8-bit bidirectional data bus (d0Cd7), seven address line inputs (a0Ca6), three control inputs (rd /ds, wr /r/w , cs ), one interrupt request output (int ) and a 4-channel dma interface (drqta, drqra, dacka , drqtb, drqrb, dackb ). mode input pins (strapping options) allow the bus interface to be configured for either siemens/ intel or motorola environment. generally, there are two types of transfers occurring via the system bus: C command/status transfers, which are always controlled by the cpu. the cpu sets the operation mode (initialization), controls function sequences and gets status information by writing or reading the hscxs registers (via cs , wr or rd , and register address via a0-a6). C data transfers, which are effectively performed by dma without cpu interaction using the hscxs dma interface (dma mode). optionally, interrupt controlled data transfer can be done by the cpu (interrupt mode). memory cpu cs system bus hscx data drqta, drqtb, dma controller command status serial channel int its00947 a b channel serial drqra, drqrb, dacka dackb
semiconductor group 18 82525 82526 82525 82526 sab sab saf saf specific applications hscx with sab 8051 microcontroller for cost-sensitive applications, the hscx can be interfaced with a small sab 8051 microcontroller system (without dma support) very easily as shown in figure 3 . figure 3 hscx with 8051 cpu although the hscx provides a demultiplexed bus interface, it can optionally be connected directly to the local multiplexed bus of sab 8051 because of the internal address latch function (via ale, compatibility to sab 82520 hscc). the address lines a0 a6 must be wired externally to the data lines d0 d6 (direct connection) in this case. intel bus mode is selected connecting im1 pin to low ( v ss ). since data transfer is controlled by interrupt, the dma acknowledge inputs (dacka , dackb ) are connected to v dd (+ 5 v). int0 rd wr ale a8 - a15 ad0 - ad7 int rd wr ale cs a0 - a6 d0 - d7 dacka dackb channel b channel a ad0 - ad7 ale wr rd latch a8 - a15 memory common bus its00948 cpu sab 8051 sab 82525 hscx a0 - a15, d0 - d7 im1 +5 v v +5
semiconductor group 19 82525 82526 82525 82526 sab sab saf saf hscx with sab 80188 microprocessor a system with minimized additional hardware expense can be with a sab 80188 microprocessor as shown in figure 4. figure 4 hscx with sab 80188 cpu the hscx is connected to the demultiplexed system bus. data transfer for one serial channel can be done by the 2-channel on-chip dma controller of the sab 80188, the other channel is serviced by interrupt. since the sab 80188 does not provide dma acknowledge outputs, data transfer from/to hscx is controlled via cs , rd or wr address information (a0 a6) and the dacka , dackb inputs are not used. this solution supports applications with a high speed data rate in one serial channel with minimum hardware expense making use of the on-chip peripheral functions of the sab 80188 (chip select logic, interrupt controller, dma controller). drq1 drqra system system bus its00949 drqta drq0 d0 - d7 a0 - a6 serial channel a serial channel b d0-d7 a0-a6 memory latches transceiver a8 - a15 ad0 - ad7 sab 80188 cpu hscx sab 82525 intn pscn +5 v dacka ale dackb cs +5 v int im1
semiconductor group 20 82525 82526 82525 82526 sab sab saf saf hscx with sab 80186 microprocessor and sab 82258 advanced dma controller (adma) in applications, where two high-speed channels are required, a 16-bit system with sab 80186 cpu and sab 82258 adma is suitable. this is shown in figure 5. figure 5 hscx with sab 80186 cpu/sab 82258 adma hlda drqra system system bus its00950 drqta hold d0 - d7 a0 - a6 serial channel a serial channel b d0 - d7 a0 - a6 memory latches transceiver ad0 - ad15 sab 80186 cpu hscx sab 82525 intn pscn dacka dackb cs +5 v int im1 s0 - s2 adma sab 82258 dreq0 dreq1 bus control & dack0 dack1 dreq3 dreq2 drqtb drqrb dack3 dack2 & ad0 - ad15 s0 - s2
semiconductor group 21 82525 82526 82525 82526 sab sab saf saf the four selector channels of adma are used for serving the four dma request sources of hscx, allowing very high data rates at both the system bus and the serial channels. another big advantage of the adma is its data chaining feature, providing an optimized memory management for receive and transmit data. recording the hscx, a linked chain of 32 byte deep buffers can be set up, which are subsequently filled with the contents of the hscxs fifos during reception. not used buffers can be saved and linked to another buffer chain reserved for the reception of the next frame. as a result, its not necessary to reserve a very large space in system memory, determined by the maximum frame length of every received frame. in this example, the adma works directly at the cpus local bus and shares the same bus interface logic (address latches, transceivers, bus controller) with the sab 80186. since one dma acknowledge line is provided for each dma request, two dack outputs must be anded together for input to the hscx. the hscxs data lines are connected to the lower half of the system data bus (d0 d7) and the address lines to a1 a7, thus (from the cpus point of view) all internal register addresses must be multiplied by two (even register addresses only). e.g. cmdr register: hscx address 61 h < = > system address c2 h . 1.3 functional description general the hscx distinguishes from other low level hdlc devices by its advanced characteristics. the most important are: beyond the point-to-point configurations, the hscx directly enables point-to-multipoint or multimaster configurations without additional hardware or software expense. in point-to-multipoint configurations, the hscx can be used as a master as well as a slave station. even when working as slave station, the hscx can initiate the transmission of data at any time. an internal function block provides means of idle and collision detection and collision resolution, which are necessary if several stations start transmitting simultaneously. these features were integrated to support multimaster configurations. enlarged support of link configurations.
semiconductor group 22 82525 82526 82525 82526 sab sab saf saf figure 6 link configuration itc02695 cxd txd rxd hscx master 1 controller cxd txd rxd hscx cxd txd rxd hscx cxd txd rxd hscx rxd - receive data cxd - collision data txd - transmit data master 2 master 3 master n controller controller controller itc02694 cxd txd rxd hscx slave 1 controller cxd txd rxd hscx 2 slave cxd txd rxd hscx 3 slave cxd txd rxd hscx n slave master hscx txd rxd controller rxd - receive data cxd - collision data txd - transmit data controller controller controller itc02705 txd rxd hscx controller rxd - receive data txd - transmit data hscx rxd txd controller point-to-point configuration point-to-multipoint configuration multimaster configuration
semiconductor group 23 82525 82526 82525 82526 sab sab saf saf support of layer-2 functions by hscx beside those bit-oriented functions usually supported with the hdlc protocol, such as bit stuffing, crc check, flag and address recognition, the hscx provides a high degree of procedural support. in a special operating mode (auto-mode), the hscx processes the information transfer and the procedure handshaking ( i -, and s-frames of hdlc protocol) autonomously. the only restriction is, that the window size (= number of outstanding unacknowledged frames) is limited to 1, which will be sufficient in most applications. the communication procedures are mainly processed between the communication controllers and not between the processors. thus the dynamic load of the cpu and the software expense is largely reduced. figure 7 procedural support in auto-mode its05502 hscx hscx p s frame frame i frame u p the cpu is informed about the status of the procedure and has to manage the receive and transmit data mainly. in order to maintain cost effectiveness and flexibility, such functions as link setup/disconnection and error recovery in case of protocol errors (u-frames of hdlc protocols) are not implemented in hardware and must be done by users software. telecom specific features in a special operating mode, the hscx can transmit or receive data packets in one of up to 64 time-slots of programmable width (clock mode 5). furthermore, the hscx can transmit or receive variable data portions within a defined window of one or more clock cycles, which has to be selected by an external strobe signal (clock mode 1). these features make the hscx especially suitable for all applications using time division multiplex methods, such as time-slot oriented pcm systems, systems designed for packet switching, or in isdn applications. fifo buffers to efficient transfer of data packets. a further speciality of hscx are the fifo buffers used for the temporary storage of data packets transferred between the serial communications interface and the parallel system bus. also because of the overlapping input/output operation (dual-port behaviour), the maximum message length is not limited by the size of the buffer. together with the dma capability, the dynamic load of the cpu is drastically reduced by transferring the data packets block by block via direct memory access. the cpu only has to initiate the data transmission by the hscx and determine the status in case of completely received frames, but is not involved in data transfers.
semiconductor group 24 82525 82526 82525 82526 sab sab saf saf the hdlc controller of each channel can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be effected in a very flexible way, which satisfies most requirements. there are 6 different operating modes which can be set via the mode register. 2 operating modes characteristics: window size 1, arbitrary message length, address recognition. the hscx processes autonomously all numbered frames (s-, i -frames) of an hdlc procedure. the hdlc control field, data in the i-field of the frames and an additional status byte is temporarily stored in the rfifo. the hdlc control field as well as additional information can also be read from special registers (rhcr, rsta). according to the selected address mode, the hscx can perform a 2-byte or 1-byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value fe h or fc h (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r), dependent on the setting of the cri bit in rah1, and will be excluded from the address comparison. similary, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the hscx can be called (addressed) with 6 different address combinations, however, only the logical connection identified through the address combination rah1, ral1 will be processed in the auto-mode, all others in the non-auto mode. hdlc frames with address fields that do not match with any of the address combinations, are ignored by the hscx. in case of a 1-byte address, ral1 and ral2 will be used as compare registers. according to the x.25 lapb protocol, the value in ral1 will be interpreted as command and the value in ral2 as response. after receiving a frame it takes 5 clock cycles to generate the response frame and to start transmission. 2.1 auto-mode (mode: mds1, mds0 = 00) characteristics: address recognition, arbitrary window size. all frames with valid addresses (address recognition identical to auto-mode) are forwarded directly to the system memory. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. the hdlc control field and additional information can also be read from special registers (rhcr, rsta). in non-auto mode, all frames are treated similarly. 2.2 non-auto mode (mode: mds1, mds0 = 01)
semiconductor group 25 82525 82526 82525 82526 sab sab saf saf characteristics: address recognition high byte only the high byte of a 2-byte address field will be compared. the whole frame except the first address byte will be stored in rfifo. ral1 contains the second and rhcr the third byte following the opening flag. 2.3 transparent mode 1 (mode: mds1, mds0, adm = 101) characteristics: no address recognition no address recognition is performed and each frame will be stored in the rfifo. ral1 contains the first and rhcr the second byte following the opening flag. 2.4 transparent mode 0 (mode: mds1, mds0, adm = 100) characteristics: fully transparent in extended transparent modes, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, bit- stuffing mechanism. this allows user specific protocol variations or the usage of character oriented protocols (such as ibm bisync). data transmission is always performed out of the xfifo. in extended transparent mode 0 (adm = 0), data reception is done via the ral1 register, which always contains the actual data byte assembled at the rxd pin. in extended transparent mode 1 (adm = 1), the receive data are additional shifted into the rfifo. also refer to chapter 6.1 and 6.2. 2.5 extended transparent modes 0; 1 (mode: mds1, mds0 = 11)
semiconductor group 26 82525 82526 82525 82526 sab sab saf saf 2.6 receive data flow (summary) the following figure gives an overview of the management of the received hdlc frames as affected by different operating modes. figure 8 receive data flow of hscx itd00228 flag addr ctrl i crc flag address control data status auto/16 rah1, 2 ral1, 2 rfifo rhcr rsta 001 adm mds0 mds1 rsta rhcr rfifo x ral1, 2 0 0 0 auto/8 auto/16 011 rah1, 2 ral1, 2 rfifo rhcr rsta auto/8 010 x rfifo rhcr rsta transparent 101 rah1, 2 rfifo rhcr rsta 100 rfifo rsta non non ral1, 2 ral1 1 0 transparent ral1 rhcr mode note: in case of on 8 bit address, the control field starts here! description of symbols: compared with (register) processed autonomously stored (fifo, register)
semiconductor group 27 82525 82526 82525 82526 sab sab saf saf 82525 82526 82525 82526 sab sab saf saf two different types of frames can be transmitted: 2.7 transmit data flow figure 9 transmit data flow of hscx itd00229 flag addr ctrl i crc flag address control data checkram xfifo xad1 xad2 xfifo *1 *1 transmit transparent frame (xtf) transmit i-frame (xif) *1 optional checkram handling in version 2 upward i -frames and C transparent frames C as shown below. for i -frames (command xif via cmdr register), the address and control fields are generated autonomously by the hscx and the data in the xfifo is entered into the information field of the frame. this is possible only, if the hscx is operated in the auto-mode. for transparent frames (command xtf via cmdr register), the address and the control fields have to be entered in the xfifo as well. this is possible in all operating modes and used also in auto-mode for sending u-frames.
semiconductor group 28 82525 82526 82525 82526 sab sab saf saf when operating in the auto-mode, the hscx offers a high degree of procedural support. in addition to address recognition, the hscx autonomously processes all (numbered) s- and i-frames (prerequisite window size 1) with either normal or extended control field format (modulo 8 or modulo 128 sequence numbers C selectable via rah2 register). 3 procedural support (layer-2 functions) updating of transmit and receive counter C evaluation of transmit and receive counter C in addition, all unnumbered frames are forwarded directly to the processor. the following functions will be performed: processing of s commands C flow control with rr/rnr C generation of responses C transmitting of s commands, if acknowledgement is missing C continuous status query of opposite termination after rnr has been received C programmable timer/repeater functions. C recognition of protocol errors C additional logic connections can be operated in parallel by software. the logic link can be initialized by software at any time (rhr). initially (i.e. after reset), the lap controllers of the two serial channels are configured to function as a combined station, where they autonomously perform a subset of the x.25 lapb/ isdn lapd protocol. 3.1 full-duplex lapb/lapd operation the logic processing of received s-frames is performed by the hscx without interrupting the m c. the m c is merely informed by interrupt with respect to status changes in the opposite station (receive ready/not receive ready) and protocol errors (unacceptable n(r) or s-frame with i field). reception of frames i -frames are also processed autonomously and checked for protocol errors. the i -frame will not be accepted in the case of n(s) error (no interrupt is forwarded to the m c), but is immediately confirmed by an s response. if the m c sets the hscx into a "receive not ready" status, an i -frame will not be accepted (no interrupt) and an rnr response is transmitted. u-frames are always stored in the rfifo and forwarded directly to the m c. the logic sequence and the reception of a frame in the auto-mode is illustrated in figure 10. note: the state variables n(s), n(r) are evaluated within the window size, i.e. the hscx checks only the isb of the receive and transmit counter regardless of the selected modulo count.
semiconductor group 29 82525 82526 82525 82526 sab sab saf saf the hscx autonomously transmits s commands and s responses in the auto-mode. either transparent or i -frames can be transmitted by the user. the software timer has to be operated in the internal timer mode to transmit i -frames. after the frame has been transmitted, the timer is self-started, the xfifo is inhibited, and the hscx waits for the arrival of a positive acknowledgement. this acknowledgement can be provided by means of an s- or i -frame. transmission of frames message has been acknowledged as positive (xpr interrupt) C message must be repeated (xmr interrupt) C transparent frames can be transmitted in all operating modes. after the transmission of a transparent frame the xfifo is immediately enabled, which is confirmed by interrupt (xpr). in this case, time monitoring can be performed with the timer in the external timer mode. note: the internal timer mode should only be used in the auto-mode. response has not been received (tin interrupt) C upon arrival of an rnr frame, the software timer is started and the status of the opposite station is polled periodically after expiration of t 1 , until the status "receive ready" has been detected. the user is informed accordingly via interrupt. if no response is received after n1 times an interrupt will be generated (tin interrupt). as a result, the process will be terminated as illustrated in figure 11 . if no positive acknowledgement is received during time t 1 , the hscx transmits an s command (p = 1), which must be followed by an s response (f = 1). if the s response is omitted, the process is performed n1 times before it is terminated. upon the arrival of an acknowledgement or after the completion of this poll procedure the xfifo is enabled and an interrupt is forwarded to the m c. interrupts may be triggered by the following:
semiconductor group 30 82525 82526 82525 82526 sab sab saf saf figure 10 processing of received frames in auto-mode itd00230 command with p = 1 ? y ? ready rec. n f = p trm rr activ rec. set rrnr response pce int : 1 response trm rnr f = p ? overflow data n : int rme set rdo response trm rr f = p rme int : n y y n y rec. ready : int rme n set rdo data overflow ? n y acknowledge reset wait for y y ? acknowledge wait for n y : int xmr reset wait for acknowledge acknowledge reset wait for alls int : response f = 1 ? n (s) + 1 n(r) = v n y wait for acknowledge ? n n y ? crc error set crce n n set rab aborted ? y u frame 1 y prot. error ? n pce int : : int rme set crce n ? crc error y set rab aborted ? n y i frame n 1 y prot. error ? n or abort crc error y rnr ? 1 reset rrnr ? , y crc error or abort n ? prot. error y n : int pce srej rej rr , 1 y v (s) v = (s) + 1 y ? alls : int n(r) (s) + 1 = v ? v (s) = (s) v + 1 alls int : = v n(s) (r) + 1 ? (r) (r) v = v + 1
semiconductor group 31 82525 82526 82525 82526 sab sab saf saf figure 11 timer procedure/poll cycle itd00231 wait for acknowledge set ? ? 2 ? with f = 1 response wait for acknowledge ? rrnr n nn y y n 2 y y = ? (r) (s) + 1 v n y n 1 t load rec.rnr rec. rr i rec. frame t proc. activ tin int : 1 load t 1 y ? ready rec. n command, p = 1 trm rr trm rnr command, p = 1 n1 n1 - 1 = n ? y y ? n n1 = 7 n1 = 0 run out 1 2 2 load t 1 trm rr/rnr cmdr ; sti command p = 1 trm i frame acknowledge set wait for inactiv t proc. 1 rnr set rrnr rec. 1 t load n 1 load n 1
semiconductor group 32 82525 82526 82525 82526 sab sab saf saf examples the interaction between the hscx and the cpu during the transmission and reception of i -frames is illustrated in figure 12, the flow control with rr/rnr during the reception of i -frames in figure 13, and during the transmission of i -frames in figure 14. both the sequence of the poll cycle and protocol errors are illustrated in figure 15 . figure 12 transmission/reception i -frames figure 13 flow control/reception itd00232 rme rme wfa transmit with frame i confirm i frame alls alls wfa reception frame i transmit frame i rr (1) (0.0) i rr (1) i (0.1) (1.1) i (1.2) i rr (2) xpr xpr itd00234 rnr rme xrnr rnr (0) rr (0.0) i rr (0) p = 1 rr (0) f = 1 rr (0) p = 1 rr (0) f = 1 i (0.0) rr (1)
semiconductor group 33 82525 82526 82525 82526 sab sab saf saf figure 14 flow control/transmission figure 15 s commands/protocol error itd00233 rr (0) f = 1 rnr rsc(rnr) rsc (rr) xmr wfa t1 t1 rr (0) p = 1 rnr (0) f = 1 rnr (0) i (0.0) rr (0) p = 1 xpr alls itd00235 t1 t1 t1 rr p = 1 poll cycle protocol error i rr (0) p = 1 rr (1) rr (2) alls pce tin wfa alls rr (0) wfa rr p = 1 (0.0) xpr
sab 82525 sab 82526 saf 82525 saf 82526 semiconductor group 34 901.90 3.2 half-duplex sdlc-nrm operation the lap controllers of the two serial channels can be configured to function in a half-duplex normal response mode (nrm), where they will operate as a slave (secondary) station, by setting the nrm bit in the xbch register of the respective channel. in contrast to the full-duplex lapb/lapd operation, where the combined (primary + secondary) station transmits both commands and responses and may transmit data at any time, the nrm mode allows only responses to be transmitted and the secondary station may transmit only when instructed to do so by the master (primary) station. the hscx gets the permission to transmit a frame from the primary by an s-, or i -frame with the poll bit (p) set! the nrm mode can be profitably used in a point-to-multipoint configuration with a fixed master-slave relationship and avoids collisions on the common transmit line. its the responsibility of the master station to poll the slaves periodically and to process the error recovery. prerequisite for nrm operation is: mode: mds0, mds1, adm = 000 mode: tdm = 0 xad1 = xad2 = ral1 = ral2 ? (address of secondary) note: the broadcast address may be programmed in ral2 if broadcasting is required. reception of frames the reception of frames functions equally to the lapb/lapd operation. transmission of frames the hscx does not transmit s-, or i -frames if not instructed to do so by the primary station sending an s-, or i -frame with the poll bit set. the hscx can be prepared to send an i -frame by the cpu issuing an xif command (via cmdr) at any time. the transmission of the frame, however, will not be initiated by the hscx prior to the reception of either a rr, or i -frame with a poll bit set (p = 1). after the frame has been transmitted (with the final bit set), the xfifo is inhibited and the hscx waits for the arrival of a positive acknowledgement. auto-mode with 8-bit address field selected external timer mode same transmit and receive addresses, since only responses can be transmitted, i.e.
semiconductor group 35 sab 82525 sab 82526 saf 82525 saf 82526 since the on-chip timer of the hscx must be operated in the external mode (a secondary may not poll the primary for acknowledgements), time supervisory must be done by the primary station. upon the arrival of an acknowledgement the xfifo is enabled and an interrupt is forwarded to the cpu, either the C message has been acknowledged as positive (xpr interrupt), or the C message must be repeated (xmr interrupt). additionally, the timer can be used under cpu control to provide timer recovery of the secondary if no acknowledgements are received at all. note: the transmission of transparent frames is possible only if the permission to send is achieved by an s-frame (p = 1) or i -frame.
semiconductor group 36 sab 82525 sab 82526 saf 82525 saf 82526 examples a few examples of hscx/cpu interaction in case of nrm mode are provided in figure 16 to figure 19. figure 16 no data to send figure 17 data reception/transmission itd00236 rr (0) f = 1 rr (0) p = 1 primary hscx secondary (0,1) f = 1 (0,0) p = 1 itd00237 (1,1) p = 1 rr (2) f = 1 alls rme xif i i i
semiconductor group 37 sab 82525 sab 82526 saf 82525 saf 82526 figure 18 data transmission (no error) figure 19 data transmission (error) (0,0) f = 1 rr (0) p = 1 itd00238 rr (1) p = 0 alls xif i itd00239 xif read exir rr (0) p = 1 i (0.0) f = 1 xmr t rr (0) p = 1 rr (0) f = 1
semiconductor group 38 sab 82525 sab 82526 saf 82525 saf 82526 3.3 error handling depending on the error type, erroneous frames are handled according table 1. table 1 error handling frame type error type generated response generated interrupt rec. status i crc error aborted unexpec. n(s) unexpec. n(r) C C s-frame C rme rme C pce crc error abort C s crc error aborted unexpec. n(r) with i-field C C C C C C pce pce C C note: the station variables (v(s), v(r)) are not changed. 4 cpu interface 4.1 register set the communication between the cpu and the hscx is done via a set of directly accessible 8-bit registers. the cpu sets the operating modes, controls function sequences, and gets status information by writing or reading these registers (command/status transfer). complete information concerning the register functions is provided in detailed register description. the most important functions programmable via these registers are: C setting of operating and clocking modes C layer-2 functions C data transfer modes (interrupt, dma) C bus mode C dpll mode C baudrate generator C test loop each of two serial channels of hscx is controlled via an equal, but totally independent register file (channel a and channel b). 4.2 data transfer modes data transfer between the system memory and the hscx for both transmit and receive direction is controlled by either interrupts (interrupt mode), or independently from cpu interaction using the hscxs 4-channel dma interface (dma mode). after reset, the hscx operates in interrupt mode, where data transfer must be done by the cpu. the user selects the dma mode by setting the dma bit in the xbch register. both channels can be independently operated in either interrupt or dma mode (e.g. channel a-dma, channel b-interrupt).
semiconductor group 39 sab 82525 sab 82526 saf 82525 saf 82526 4.3 interrupt interface special events in the hscx are indicated by means of a single interrupt output, which requests the cpu to read status information from the hscx, or, if interrupt mode is selected, transfer data from/to hscx. since only one int request output is provided, the cause of an interrupt must be determined by the cpu reading the hscxs interrupt status registers (ista, exir). the structure of the interrupt status registers is shown in figure 20. figure 20 hscx interrupt status registers
semiconductor group 40 sab 82525 sab 82526 saf 82525 saf 82526 five interrupt indications can be read directly from the ista register and another six interrupt indications from the extended interrupt register (exir). after the hscx has requested an interrupt by setting its int pin to low, the cpu must first read the interrupt status register of channel b (ista-b) in the associated interrupt service routine. the three lowest order bits (bit 2-0) of ista-b (ica, exa, exb) point are set to those registers in which the actual interrupt source is indicated. it is possible that several interrupt sources are indicated referring to one interrupt request (e.g. if the ica bit is set, at least one interrupt is indicated in the ista register of channel a). an interrupt source from channel b is implicitly indicated by bits 7-3 of ista-b; therefore these bits must also always be checked. the int pin of the hscx remains active until all interrupt sources are cleared by reading the corresponding interrupt register. therefore it is possible that the int pin is still active when the interrupt service routine is finished. for some interrupt controllers or cpus it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. this can be done by masking all interrupts at the end of the interrupt service routine (writing ff h into the mask register) and write back the old mask to the mask register. the hscx interrupt sources can be logically grouped into C receive interrupts, C transmit interrupts, and C special condition interrupts. each interrupt indication of the ista registers can be selectively masked by setting the respective bit in the mask register. the following tables give a complete overview of the individual interrupt indications and the cause of their activation as well as specific restrictions (marked with * ).
semiconductor group 41 sab 82525 sab 82526 saf 82525 saf 82526 table 2 receive interrupts receive interrupts rpf receive pool full (ista) *only activated in interrupt mode! activated as soon as 32-bytes are stored in the rfifo but the message is not yet completed. rme receive message end (ista) interrupt mode: activated if either one message up to 32 bytes or the last part of a message with more than 32 bytes is stored in the rfifo, i.e. after the reception of the crc and closing flag sequence. dma mode: activated after the complete message has been read out by the dma controller. rfo receive frame overflow (exir) activated if a complete frame could not be stored due to occupied rfifo, i.e. the rfifo is full and the hscx has detected the start of a new frame. rfs receive frame start (exir) *only activated if enabled by setting the rie bit in ccr2 register. activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after an rfs interrupt, the contents of C rhcr C ral1 C rsta C bit 3-0 are valid and can be read by the cpu.
semiconductor group 42 sab 82525 sab 82526 saf 82525 saf 82526 table 3 transmit interrupts transmit interrupts xpr transmit pool ready (ista) activated whenever a 32-byte fifo pool is empty and accessible to the cpu, i.e. C following a xres command via cmdr. interrupt mode: repeatedly during frame transmission started by xtf or xif command, and no end of message indication (xme command) has been issued yet by the cpu, C after the end-of-message indication when frame transmission of a transparent frame is completed (i.e. crc and closing flag sequence are shifted out), auto-mode: if an i -frame has been positively acknowledged by the opposite station. xmr transmit message repeat (exir) auto-mode: activated if the last transmitted i -frame has to be repeated due to the reception of a negative acknowledgement (s-, or i -frame with unaccording receive sequence number) of the opposite station. bus configuration: a collision has occurred after sending the 32nd data byte of a message. point-to-point configuration: cts has been withdrawn after sending the 32nd data byte. xdu transmit data underrun (exir) activated if the xfifo holds no further data, i.e. all data has been shifted out via the serial t d pin, but no end of message (eom) indication has been detected by the hscx. the eom indication is supplied either C by a xme command from the cpu in interrupt mode, C or by checking the pre-programmed transmit byte count (via xbch, xbcl) against the actual amount of data bytes shifted out in dma mode.
semiconductor group 43 sab 82525 sab 82526 saf 82525 saf 82526 table 4 special condition interrupts special condition interrupts layer 2-specific * activated only if the "auto" operating mode has been selected via mode register) rsc receive status change activated after a status change of the opposite stations receiver has been detected (receiver ready/receiver not ready) due to the reception of a C rr frame, if receiver was not ready, or C rnr frame, if receiver was ready. pce protocol error activated if a protocol violation has been detected due to the reception of C an s-, or i -frame with incorrect n(r), C an s-frame containing an i-field. internal timer tin timer interrupt (ista) activated if the internal timer and repeat counter has been expired (see description of timr register in chapter 8). external pin csc cts status change (exir) * only activated if enabled by setting the cie bit in the ccr2 register. 4.4 dma interface the hscx comprises a 4-channel dma interface for fast and effective data transfers. for both serial channels, a separate dma request output for transmit (drqt) and receive direction (drqr) as well as a dma acknowledgement (dack ) input is provided. the hscx activates the drq line as long as data transfers are needed from/to the specific fifo (level triggered demand transfer mode of dma controller). its the responsibility of the dma controller to perform the correct amount of bus cycles. either read cycles will be performed if the dma transfer has been requested from the receiver, or write cycles if dma has been requested from the transmitter. if the dma controller provides a dma acknowledge signal (input to the hscxs dack pin), each bus cycle implicitly selects the top of the specific fifo and neither address (via a0-a6) nor chip select need to be supplied ( i /o to memory transfers). if no dack signal is supplied, normal read/write operations (providing addresses) must be performed (memory to memory transfers). the hscx deactivates the drq line immediately after the last read/write cycle of the data transfer has started.
semiconductor group 44 sab 82525 sab 82526 saf 82525 saf 82526 hscx supports target synchronous as well as source synchronous dma transfer. in source synchronous dma transfer mode a dma cycle is started when an active level occurs an the dma request line. this request is controlled by the source (transfer peripheral device ? memory). first of all the data is read out of the peripheral device. during the second clock cycle it is writ- ten into the memory according to the target address. if there is target synchronous dma transfer the dma cycle is started when there is an active level on the dma request line. the request is controlled by the target (transfer memory ? peripheral). first of all the data is read from the memory. during the second clock cycle it is written into the peripheral ic. the dma request line continues being activated until it is reset by a write cycle to a peripheral device ic. itd02697 t1 t2 t3 t4 t1 t2 t3 t4 t drhsys t clrl t invcl clockout drq rd (fifo) wr (memory) f clkout t clcl t clrl t invcl t drhsys max 8 mhz 125 ns 44 ns 15 ns 316 ns ns 188 ns 15 ns 37 ns 80 mhz 12.5 ns 141.5 ns 15 ns 31 ns 62.5 mhz 16 invcl t - t clcl - t clrl x 3 = invcl t - clrl t - t4 + t3 = max drhsys t + t2
semiconductor group 45 sab 82525 sab 82526 saf 82525 saf 82526 if you use the write signal instead of the chip select signal in order to reset the dma request you gain some time. the extra circuit is just an and gate. the first input of the and gate is connected to the dma request line of the peripheral ic; the second input is connected to the chip select line. the and gates output is the dma request signal for the 80(c)188. theoretically, the request line of an 80(c)188, for example, would still be active when the de- termination is made and dma cycles would be performed permanently. therefore the decision of the dma request line is delayed; it is already made two clock cycles before the end of the write cycle. if no wait-states are inserted the decision is made at the end of the t2 clock cycle. due to the fact that the write signal will be valid at the beginning of t2 there is only little time left for resetting the dma request line. itd02698 t1 t2 t3 t4 t1 t2 t3 t4 t drhsys t cvctv t invcl clockout drq rd (memory) wr (fifo) t drhsys max =t2- t cvctv - t invcl f clkout t clcl t cvctv t invcl t drhsys max 8 mhz 125 ns 56 ns 15 ns 54 ns ns 18 ns 15 ns 47 ns 80 mhz 12.5 ns 16.5 ns 15 ns 31 ns 62.5 mhz 16 its02699 & drq pcs 80(c)188 hscx drqtx cs
semiconductor group 46 sab 82525 sab 82526 saf 82525 saf 82526 the circuit mentioned above results in a slower data transfer with the hscx. hscx usually performs block transfers. the block length is up to 32 bytes. the dma request line of the ic remains active as long as more data are needed. having transmitted the last byte the dma request is being reset. using the additional circuit the dma request line will be active at least shortly before t4. so the next dma cycle will be started four (instead of two) clock cycles later. therefore the maximum transmission rate is reduced from 1.25 mbyte/s to 1.04 mbyte/s (clock rate: 12.5 mhz). for more information refer to chapter 7.2 (data transmission: dma mode), chapter 7.3 (data reception: dma mode), and appendix c (application example hscx with 80(c)188 using dma). itd02700 t1 t2 t3 t4 t1 t2 t3 t4 t drhsys t clcsv t chcsx clockout drqtx rd (memory) cs (fifo) wr (fifo) t drhsys max = t2 + t3 - t cvctv + t chcsx f clkout t clcl t cvctv t chcsx t drhsys max 8 mhz 125 ns 56 ns 5 ns 261 ns ns 158 ns 5 ns 47 ns 80 mhz 12.5 ns 130 ns 5 ns 31 ns 62.5 mhz 16 t4/2 + drq cvctv t
semiconductor group 47 sab 82525 sab 82526 saf 82525 saf 82526 4.5 fifo structure in both transmit and receive direction 64-byte deep fifos are provided for the intermediate storage of data between the serial interface and the cpu interface. the fifos are divided into two halves of 32-bytes, where only one half is accessible to the cpu or dma controller at any time. the organization of the receive fifo (rfifo) is such, that in the case of a frame at most 64 bytes long, the whole frame may be stored in the rfifo. after the first 32 bytes have been received, the hscx prompts to read the 32-byte block by means of interrupt or dma request (rpf interrupt or activation of drqr line). this block remains in the rfifo until a confirmation is given to the hscx acknowledging the transfer of the data block. this confirmation is either a rmc (receive message complete) command via the cmdr register in interrupt mode, or is implicitly achieved in dma mode after 32-bytes have been read from the rfifo. as a result, its possible in interrupt mode, to read out the data block any number of times until the rmc command is issued. the configuration of the rfifo prior to and after acknowledgement is shown in figure 21. figure 21 configuration of rfifo (long frames) itd01582 32 inaccessible accessible 32 a) prior to acknowledgement b) after acknowledgement block b + 1 block b free b + 1 block bytes bytes
semiconductor group 48 sab 82525 sab 82526 saf 82525 saf 82526 if frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32- byte data blocks via interrupt or dma. in the case of several shorter frames, up to 17 may be stored in the hscx. if the accessible half of the rfifo contains a frame i (or the last part of frame i), up to 16 short frames may be stored in the other half (i + 1,. . ., i + n) meanwhile, prior to frame i being fetched from the rfifo. this is illustrated in figure 22. for a description of a transmit and receive sequence in both interrupt or dma mode, please refer to chapter 7.2 and 7.3. figure 22 configuration of rfifo (short frames) note: the number of 17 frames applies e.g. for the hscx operating in the auto or non-auto mode (address recognition), and short frames only containing the hdlc address and control field are received. since the address is not stored, the control field is always stored first in the rfifo, and an additional status byte is always appended at the end of each frame in the rfifo, these frames will occupy two bytes. 32 inaccessible accessible 32 a) prior to acknowledgement b) after acknowledgement frame last part of frame frame i + n i + 1 frame i + n frame i + 2 frame i + 1 16 n < 0 itd00486 bytes bytes i _ <
semiconductor group 49 sab 82525 sab 82526 saf 82525 saf 82526 5.1 clock modes the hscx includes an internal oscillator (osc) as well as independent baudrate generator (brg) and digital phase locked loop (dpll) circuitry for each serial channel. the transmit and receive clock can be either generated C externally, and supplied via the r clk and/or t clk pins, or C internally, by means of the * osc and/or brg, and * dpll, recovering the receive (and optionally transmit) clock from the received data stream if an external crystal is connected to the r clka-a clka pins. totally, there are 8 different clocking modes programmable via the ccr1 register, providing a wide variety of clock generation and clock pin functions, as shown in table 5. table 5 overview of clock modes type source generation mode clock receive clock r clk pins dpll osc externally internally 0, 1, 5 2, 3, 6, 7 4 transmit clock t clk pins r clk pins dpll brg/16 osc externally internally 0, 2, 6 1, 5 3, 7 2, 6 4 the transmit clock pins (t clk) may also output clock or control signal in certain clock modes if programmed as outputs via the ccr2 register (tio bit set). the clocking source for the dplls is always the internal brg; the scaling factor (divider) of the brg can be programmed through ccr2 and bgr registers between 1,2,4,6. . .2048. the hscx system clock is always derived from the transmit clock thus eliminating the need for additional clock sources. 5 serial interface (layer-1 functions) the two serial interfaces of the hscx provide two fully independent communications channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. clock mode 0 (external clocks) separate, externally generated receive and transmit clocks are forwarded to the hscx via their respective pins.
semiconductor group 50 sab 82525 sab 82526 saf 82525 saf 82526 clock mode 1 (receive/transmit strobes) externally generated, but identical receive and transmit clocks are forwarded via r clk pins. in addition, a receive strobe can be connected via a clk and a transmit strobe via t clk pins. the operating mode can be applied in time division multiplex applications or for adjusting disparate transmit and receive data rates. clock mode 2 (receive clock from dpll) the brg is driven with an external clock (r clk) and it delivers a reference clock for the dpll which in turn generate the receive clock. depending on the programming of the ccr2 register (tss bit), the transmit clock will be either an external clock signal (t clk) or the clock delivered by the brg divided by 16. in this case, the transmit clock can be output via t clk (ccr2 : tio = 1). clock mode 3 (receive and transmit clock from dpll) the brg is fed with an externally generated clock via r clk and supplies the reference clock for dpll, which generates both the receive and transmit clock. this clock can also be output via t clk pin. clock mode 4 (osc-direct) the receive and transmit clocks are directly supplied by the osc. in addition this clock can be output via t clk. clock mode 5 (time-slots) this operating mode has been designed for application in time-slot oriented pcm systems. the receive and transmit clock is identical for each channel and must be supplied externally via r clk pins. the hscx receives and transmits only during certain time-slots of programmable width (1. . .256 bit, via rccr and xccr registers) and location with respect to a frame synchronization signal, which must be delivered to the hscx via the a clk pin. one of up to 64 time-slots can be programmed independently for receive and transmit direction via tsar and tsax registers, and an additional clock shift of 07 bits via tsar, tsax, and ccr2 registers. together with bits xcs0 and rcs0 (lsb of clock shift), located in the ccr2 register, there are 9 bits to determine the location of a time-slot. according to the value programmed via those bits, the receive/transmit window (time-slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame synchronization signal and is active during the number of clock periods programmed via rccr, xccr (number of bits to be received/transmitted within a time-slot) as shown in figure 23.
semiconductor group 51 sab 82525 sab 82526 saf 82525 saf 82526 figure 23 location of time-slots the transmit time-slot is additionally indicated by a control signal via t clk, which output is set to log 0 during the transmit window. note: in extended transparent mode the width of the time-slots has to be n 8 bit. itd00240 time slot number tsn (6 bits) clock shift cs (3 bits) 9 bits 2 xcs 1 0 rcs0 1 rcs rcs2 xcs xcs ccr 2 tsnr tsnx tsar tsax register : n time slot delay 1+ snx8 + cs (1...512 clocks) width via rccr, xccr (1...256 clocks) cd r x clk t x clk ~ ~~ ~
semiconductor group 52 sab 82525 sab 82526 saf 82525 saf 82526 rts signal in clock mode 5 when using the rts signal in clock mode 5, it has to be considered, that the rts signal is deactivated after the transmission of the second last bit (instead of the last) of a closing flag, if that second last bit is the last bit of a time-slot window. in other words, rts is inactive during the transmission of the last bit, transmitted in the next time-slot window. see figure 24 . figure 24 itd05965 int xpr int status rts txd txclk (ts,- ctrl) time-slot n time-slot n + 1 idle, interframe time-fill d = valid data bits ddd...d d last bit of a frame last bit of closing flag
semiconductor group 53 sab 82525 sab 82526 saf 82525 saf 82526 this must be considered for applications, where several transmitters are sharing the same time-slot on a non open-drain bus, e.g. a balanced bus, not using collision detection as the resolution mechanism. one such application is slave stations in a point-to-multipoint configuration sharing the same time-slot and using nrm auto-mode. thus, rts and the time- slot marker txclk cannot simply be gated to generate a driver control signal. instead the following recommendations apply: a) do not use the rts signal directly in clock mode 5 e.g. to enable drivers for txd in a balanced bus configuration. instead, use an arrangement of the type shown in the figure 25 or figure 25 itd05980 hscx txd d v dd ss v transmission line
semiconductor group 54 sab 82525 sab 82526 saf 82525 saf 82526 b) delay the rising edge of rts (e.g. for nrm mode with balanced bus). figure 26 timing diagram for recommendation b): figure 27 dq clk clk q d & 1 bus itd05966 hscx rts txclk txd _ < itd05981 int xpr int status rts (rec. b) rts ideal rts txd txclk (ts-ctrl) time-slot n time-slot n + 1 idle, interframe time-fill d = valid data bits ddd...d d last bit of a frame last bit of a closing flag
semiconductor group 55 sab 82525 sab 82526 saf 82525 saf 82526 cts signal in clock mode 5 in clock mode 5 the cts signal is evaluated not only in the time-slot window, but also between the time-slot windows. if data transmission must not be stopped, cts has to be active, even between the time-slot windows, until the transmission of the frame has been completed. in other words, a deactivation of cts stops the transmitter immediately. note: when several hdlc channels are sharing the same time-slot on a bus without using the bus collision detection, the strobe signals (axclka/b) can be used to select/ deselect particular time-slot windows for an individual hdlc channel. clock mode 6 (osc C receive clock from dpll) this clock mode equals the features of clock mode 2, with the only exception that the clock for the brg is delivered by the osc and must not be provided externally. clock mode 7 (osc C receive and transmit clock from dpll) similar to clock mode 3, but brg clock is provided by osc.
semiconductor group 56 sab 82525 sab 82526 saf 82525 saf 82526 summary the features of the different clock modes are summarized in table 6. table 6 clock modes of hscx note: 1) the maximum data rate in an externally clocked operating mode is 4.1 mbit/s. in an internally clocked operating mode with an external reference clock, or using the osc, the maximum clock rate is 12 mhz or 19.2 mhz if the scaling factor of the brg is programmed to 1. the maximum data rate will be 1200 kbit/s. 2) the ratio between the receive frequency (fr) and the transmit frequency (fx) for a channel must satisfy the condition fr/fx less than 3 in clock modes 0, 2, 6; there are no restrictions on the phase shift. slower transmit data rates can be realized with receive and transmit strobes (clock mode 1). 3) the clock modes 4, 6, 7 use the internal osc and need an external quartz crystal to be connected at the rxclk a-axclk a pins. it is not necessary to use two separate crystals for the two serial channels, instead it is sufficient to apply the crystal to channel a and provide the reference clock for channel b by externally connecting the axclka and rxclkb pins. the sab 82526 also uses the rxclk a-axclk a pins to connect to an external quartz crystal. channel configuration clock sources control sources timer source clock mode ccr1 cm2, cm1, cm0 ccr2 output via txclk tss tio brg dpll rec trm cd r-strobe x-strobe f-sync tcp 0 1 2 2 3 4 4 5 6 6 6 7 7 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 C C rxclk rxclk rxclk C C C osc osc osc osc osc C C brg brg brg C C C brg brg brg brg brg rxclk rxclk dpll dpll dpll osc osc rxclk dpll dpll dpll dpll dpll txclk rxclk txclk brg/16 dpll osc osc rxclk txclk brg/16 brg/16 dpll dpll axclk C axclk axclk axclk txclk txclk C txclk C txclk C C axclk C C C C C (tsar) C C C C C C txclk C C C C C (tsax) C C C C C C C C C C C C axclk C C C C C C C C brg/16 dpll C osc ts-control C C brg/16 C dpll txclk rxclk txclk dpll dpll osc osc rxclk txclk brg/16 brg/16 dpll dpll sab 82525 sab 82526 saf 82525 saf 82526
semiconductor group 57 sab 82525 sab 82526 saf 82525 saf 82526 normally 33 pf capacitors are used for frequencies below 10 mhz and 22 pf capacitors are used for frequencies above 10 mhz. to guarantee oscillation use the capacitances which are specified by the crystal manufacturer. its01450 rxclka axclka 5.2 clock recovery (dpll) the hscx offers the advantage of recovering the receive clock from the receive data by means of internal dpll circuitry, thus eliminating the need to transfer additional clock information via the serial link. for this purpose, the dpll is supplied with a reference clock from brg which is 16 times the data clock rate (clock mode 2, 3, 6, 7). additionally, the transmit clock may be obtained dividing the output of the brg by a constant factor of 16 (clock mode 2, 6; tss bit in ccr2 set) or also directly from the dpll (clock mode 3, 7). figure 28a the dpll circuits implemented in the hscx are optimized with respect to the hdlc protocol. the main task of the dpll is to derive a receive clock and to adjust its phase to the incoming data stream in order to enable the bit sampling in the middle of a bit-cell with the falling edge of the receive clock. for this purpose, edges in the receive data, indicating the begin of a bit- cell, are necessary. when using the nrzi encoding, the zero insert/zero delete method ensures that a sufficient number of edges occur in the data stream during the reception of an hdlc frame. furthermore a completely new "one insertion" mechanism has been implemented with the hscx, which also guarantees sufficient number of edges when using nrz encoding (especially for bus configurations, see chapter 6.5 for details). itt06028 interference rejection rxd dpll clk 1 rec. data 1
semiconductor group 58 sab 82525 sab 82526 saf 82525 saf 82526 the following functions have been implemented to facilitate a high-speed and reliable synchronization ( see figures 28 ). C interference rejection in the case where two or more edges appear in the data stream within a time period of 16 reference clocks, these are detected as interference without performing additional adjustments. figure 28b C phase adjustment in the case where an edge with a phase angle of 20 to 112 degrees appears in the data stream within the time window, the phase will be adjusted by 1/16 of the data clock. figure 28c itt00241 rec. data 1 0 dpll clk phase adjustment d x r f f f its06029 dpll receiver receive clock receive data reference clock 16 data clock rate = x nominal
semiconductor group 59 sab 82525 sab 82526 saf 82525 saf 82526 C phase shift in the case the dpll detects an edge in the data stream in the range of dpll count 5 to 10 (phase shift) and this is the only one in the assumed bit cell period, then the dpll receive clock phase is shifted by a certain dpll count value. figure 28d synchronization of the data clock in dpll mode: interference rejection and phase adjustment the dpll value and its corresponding phase shift in degree is listed below for the hscx versions va3 and v2.1: note: the operating characteristics of the dpll therefore allow a phase jitter of 18.75% of the frequency. hscx version dpll count phase shift va3 8 180 o v2.1 7 157,5 o itd05884 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 phase adjust phase shift + - assumed bit cell dpll input receive data dpll count dpll phase correction dpll output receive clock ++ 17 1 - phase adjust phase shift
sab 82525 sab 82526 saf 82525 saf 82526 semiconductor group 60 5.3 bus configuration beside the point-to-point configuration, the hscx effectively supports point-to-multipoint (pt- mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods. in a pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves), or in a multimaster configuration ( see figure 6 ) , data transmission can be initiated by each station over a common transmit line (bus). in case more than one station attempt to transmit data simultaneously (collision), the bus is assigned to one station by a collision- resolution procedure implemented by the hscx. the bus assignment function is based on a priority principle with both fixed and rotating priorities that enables each station to access the bus in a predeterminable time. as a result, any number of transmitters can be connected to the serial bus. prerequisites for bus operation are: C nrz encoding C or connection of data at the bus C feedback of bus information (c da/c db input) the bus configuration is selected via the ccr1 register. note: central clock supply for each station is not necessary if both the receive and transmit clock is recovered by the dpll (clock mode 7). in this case, the function of the dpll also minimizes the phase shift between the transmit clocks of the individual transmitters so that an opening flag sequence will be sufficient to allow a correct collision detection. the bus mode can be operated independently of the clock mode, e.g. also during clock mode 1 (receive and transmission strobe) or clock mode 5 (programmable time-slots).
semiconductor group 61 sab 82525 sab 82526 saf 82525 saf 82526 since a transmitted zero is given priority over a 1 due to the or connection at the bus, and since the individually combined stations in the address field of the transmitted hdlc frame differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. the frame of the transmitter with the highest temporary priority (address field) is not affected and is transmitted without interruptions. all other transmitters terminate their operation immediately. note : if a wired or connection has been realized by an external pull-up resistor without decoupling, the data output (t da/t db) can be used as an open drain output and connected directly to the c da, c db input. priority principle when the hdlc frame has been successfully transmitted by the hscx, the priority is decremented. in order to transmit an additional frame, ten successive 1s must be present on the bus. this fact is used as a criterion to ensure that the higher priority transmitters do not contain any transmit requests. it is now possible to transmit a frame and the priority can be increased again (8 successive 1s). this method offers a priority allocation based on the selection of a particular address. it also ensures that each subscriber can access the bus at a pre-determinable time. timing modes if a bus configuration has been selected, the hscx provides two timing modes, differing in the period between sending data and evaluation of the transmitted data for collision detection. timing mode 1 (ccr1: sc1, sc0 = 01) data is output with the rising edge of the transmit clock via the t d pins, and evaluated 1/2 clock period later with the falling clock edge at the c d pins. timing mode 2 (ccr1: sc1, sc0 = 11) data is output with the falling clock edge and evaluated with the next falling clock edge. thus one complete clock period is available during data output and their evaluation. note: if the bus is occupied by other transmitters and/or there is no transmit request in the hscx, log 1 will be continuously transmitted at the t da/t db output. bus access procedure the idle state of the bus is identified by eight or more successive 1s. in case of a transmit re- quest in the hscx, the frame is transmitted and the bus is identified as busy with the first zero of the opening flag (start flag). after the frame has been transmitted, the bus becomes available again by transmitting 1s. collisions during the transmitting process, the data transmitted from the hscx is compared with the data on the bus. in case an erroneous bit is detected (log 1 sent and log 0 detected, or vice versa) the frame is immediately aborted, and idle (log 1) is transmitted. transmission will be initiated again by the hscx as soon as possible.
semiconductor group 62 sab 82525 sab 82526 saf 82525 saf 82526 functions of rts output in clock modes 0, 1, 4 and 5, the rts output can be programmed via ccr2 (soc bits) to be active when a frame is being transmitted. the signal is delayed by one clock period with respect to the data output t da/t db, and marks all data bits that could be transmitted without collision. in this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. if the rts output is used to control an external driver it has to be anded with the txd pin in order to drive the first bit correctly. figure 29 request-to-send in bus operation its02701 & cxda/b txda/b rtsa/b line itt00242 collision rts td x xd c note: for regular and special rts functions refer to chapter 5.5 and 6.6.
semiconductor group 63 sab 82525 sab 82526 saf 82525 saf 82526 5.4 data encoding in the point-to-point configuration, the hscx supports both nrz and nrzi data encoding (selectable via ccr1 register). figure 30 nrz encoding/nrzi encoding during nrzi encoding, level changes are interpreted as log 0, and no changes in level as log 1. since no more than 5 successive log 1s can appear in a hdlc frame, this type of en- coding is especially suitable in clock modes, where the clock is recovered from the received data by means of the dpll circuits, because at least one transition appears within 5 clock cy- cles. thus, nrzi coding is especially recommended in clock modes 2, 3, 6, 7. data output is performed with the rising, data input with the falling clock edge. 5.5 modem control functions (rts/cts, cd) rts/cts handshaking the hscx provides two pins (rts, cts) per serial channel supporting the standard rts-cts modem handshaking procedure to control the hdlc transmitters. data output is performed with the rising clock edge, data input with the falling clock edge. a transmit request will be indicated by outputting log 0 at the request-to-send output (rtsa/ rtsb). it is also possible to program the rts outputs by software. after having received the permission to transmit (ctsa/ctsb) the hscx transmits a frame. in the case where permission to transmit is withdrawn during the transmission process, the frame is aborted (idle). after a new permission to transmit has been received and if all of the data are still available in the hscx, the terminated frame will be re-transmitted (self-recovery), without interrupting the cpu. however, if the permission to transmit is withdrawn after the 32nd byte in the information field, the transmitter and the xfifo are reset, the rts output is deac- tivated and an interrupt is generated for the m c. itt00243 0 1 1 0 0 1 1 1 0 nrzi encoding nrz encoding 0 1 1 0 1
semiconductor group 64 sab 82525 sab 82526 saf 82525 saf 82526 cts signal clock mode 5 in clock mode 5 the cts signal is evaluated not only in the time-slot "window", but also between the time-slot "windows". cts must not be disabled during the transmission of a frame. even between the time-slot "windows" cts has to be active until the transmission of the frame has been completed. thus, cts cannot be used to select/deselect particular time- slot "windows" for hscx. note: in the case where permission to transmit is not required, the ctsa/ctsb inputs can be connected directly to v ss . additionally, any state transition on the cts input pin will generate an interrupt indicated via the exir register, if this function is enabled by setting the cie bit in the ccr2 register. figure 31 rts-cts handshaking itt00244 sampling cts t clk x xd t rts ~ ~~ ~ ~ ~ ~ ~ carrier detect (cd) receiver control similar to the rts/cts control for the transmitter, the hscx supports the carrier detect modem control function for the serial receivers, if the carrier detect auto start (cas) function is programmed setting the cas bit in the xbch register. this function is always available in clock modes 0, 2, 3 via the a clk pin, and in clock modes 4, 6, 7 via the t clk pin only if it has been programmed as input clearing the tio bit in the ccr2 register. in clock mode 1 the cd function is not supported ( see table 6 for an overview). if the cas function is selected, the respective hdlc receiver is enabled and data reception is started when an high level is sampled at the cd input.
semiconductor group 65 sab 82525 sab 82526 saf 82525 saf 82526 this feature can be profitably used e.g. for: flag insertion and deletion crc generation and checking bit-stuffing mechanism. 6 special functions 6.1 fully transparent transmission and reception when programmed to the extended transparent mode via the mode register (mds1, mds0 = 11), each channel of the hscx supports fully transparent data transmission and reception without hdlc framing overhead, i.e. without in order to enable fully transparent data transfer, rac bit in mode has to be reset and ff h has to be written to xad1, xad2 and rah2. data transmission is always performed out of the transmit fifo by directly shifting the contents of the xfifo via the serial transmit data pin (t d). transmission is initiated by setting cmdr : xtf (08 h ); end of transmission is indicated by exir : exe (40 h ). in receive direction, the character currently assembled via the receive data line (r d) is available in the ral1 register. additionally, in extended transparent mode 1 (mode: mds1, mds0, adm = 111), the received data is shifted into the rfifo. user specific protocol variations the application of character oriented protocols (e.g. bisync) test purposes, line intentionally violation of hdlc protocol rules (e.g. wrong crc) character synchronization can be achieved either in clock mode 1, with an external receive strobe input to a clk pin, or clock mode 5, with a programmed time-slot and a frame synchronization signal input to a clk. using clock mode 1 or 5 multiples of 8 bits received per time-slot. 6.2 cyclic transmission (fully transparent) if the extended transparent mode is selected, the hscx supports the continuous transmission of the transmit fifos contents. after having written 1 to 32 bytes to the xfifo, the command xrep.xtf.xme via the cmdr register (bit 7. . .0 = "00101010" = 2ah) forces the hscx to repeatedly transmit the data stored in the xfifo via t d pin. the cyclic transmission continues until a reset command (cmdr : xres) is issued, after which continuous 1-s are transmitted. note: in dma-mode the command xrep, xtf has to be written to cmdr.
semiconductor group 66 sab 82525 sab 82526 saf 82525 saf 82526 sab 82525 sab 82526 saf 82525 saf 82526 6.3 continuous transmission (dma mode only) if data transfer from system memory to the hscx is done by dma (dma bit in xbch set), the number of bytes to be transmitted is usually defined via the transmit byte count registers (xbch, xbcl : bits xbc11. . .xbc0). setting the "transmit continuously" (xc) bit in xbch, however, the byte count value is ignored and the dma interface of the hscx will continuously request for transmit data any time 32 bytes can be stored in the xfifo. this feature can be used e.g. to note: if the xc bit is reset during continuous transmission, the transmit byte count becomes valid again, and the hscx will request the amount of dma transfers programmed via xbc11. . .xbc0. otherwise the continuous transmission is stopped when a data underrun condition occurs in the xfifo, i.e. the dma controller does not transfer further data to the hscx. in this case continuous 1-s (idle), without appending a crc, are transmitted. 1) the frame length includes all bytes which are stored in the rfifo. 6.4 receive length check feature the hscx offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. this feature is controlled via the special receive length check register (rlcr). the function is enabled by setting the rc (receive check) bit in rlcr and programming the maximum frame length via bits rl6. . .rl0 1) . according to the value written to rl6. . .rl0, the maximum receive length can be adjusted in multiples of 32-byte blocks as follows: max. length = (rl + 1) 32. all frames exceeding this length are treated as if they have been aborted from the opposite station, i.e. the cpu is informed via a C rme interrupt, and the C rab bit in rsta register is set! to distinguish between frames really aborted from the opposite station, the receive byte count (readable from rbch, rbcl registers) exceeds the maximum receive length (via rl6. . .rl0) by one or two bytes in this case. the check includes all data that is copied into the rfifo. it does not include the address byte (s) if address recognition is selected. it includes the rsta value in all operating modes. continuously transmit voice or data onto a pcm highway (clock mode 5/extended transparent mode), or to transmit frames exceeding the byte count programmable via xbch, xbcl (frames with more than 4095 bytes).
semiconductor group 67 sab 82525 sab 82526 saf 82525 saf 82526 6.5 one bit insertion similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the hdlc protocol, the hscx offers a completely new feature of inserting/deleting a one after seven consecutive zeros in the transmit/receive data stream, if the serial channel is operating in a bus configuration. this method is profitable if clock recovery should be performed by dpll. since only nrz data encoding is supported in a bus configuration ( see chapter 5.4 ), there are possibly long sequences without edges in the receive data stream in case of successive "0"-s received, and the dpll may loose synchronization. using the one bit insertion feature by setting the oin bit in the ccr1 register, however, it is guaranteed that at least after C 5 consecutive "1"-s a "0" will appear (bit-stuffing), and C 7 consecutive "0"-s a "1" will appear (one insertion) and thus a correct function of the dpll is ensured. note: as with the bit-stuffing, this method is fully transparent to the user, but it is not in accordance with the hdlc protocol, i.e. it can only be applied in private systems using hscx circuits exclusively. 6.6 data inversion when nrz data encoding has been selected, the hscx may transmit and receive data inverted, i.e. a "one" bit is transmitted as phys. zero (0 v) and a "zero" bit as phys. one (+ 5 v) via the t d line. this feature is selected by setting the div bit in the ccr2 register. please note that data cannot be inverted in bus mode unless you invert the t d / r d signal before it is sent into c d. itd00245 transmit receive log. data bit 1 0 phys. level 5 0 v v +
semiconductor group 68 sab 82525 sab 82526 saf 82525 saf 82526 6.8 test mode to provide for fast and efficient testing, the hscx can be operated in the test mode by setting the tlp bit in the mode register. the on-chip serial input and output (t da C r da, t db C r db) are connected generating a local loopback. r da and r db input is ignored. t da and t db remain active. as a result, the user can perform a self-test of the hdlc channels of the hscx. 6.7 special rts function beyond the regular rts function, signifying the transmission of a frame (request to send), the rts output may be programmed for a special function via soc1, soc0 bits in the ccr2 register, provided the serial channel is operating in a bus configuration in clock mode 0, 1, or 5. C if soc1, soc0 bits are set to 11; the rts output is active (= low) during the reception of a frame. C if soc1, soc0 bits are set to 10; the rts output function is disabled and the rts pin remains always high.
semiconductor group 69 sab 82525 sab 82526 saf 82525 saf 82526 7 operational description 7.1 reset the hscx is forced into the reset state if a high signal is input to the res pin for a minimum period of 1.8 m s. during reset, the hscx is temporarily in the power-up mode, and a subset of the registers is initialized with defined values. after reset, the hscx is in power down mode, and the following registers contain defined values: table 7 reset values register reset value meaning ccr1 00 h C power down mode serial port configuration; pt-pt, nrz coding, transmit data pins are open drain outputs C clock mode 0 ccr2 00 h rts pin normal function C cts and rfs interrupts disabled no data inversion mode 00 h auto-mode 1 byte address field external timer mode C receivers inactive rts output controlled by hscx, timer resolution: k = 32.768, no testloop star 48 h xfifo write enable receive line inactive no commands executing ista exir 00 h C no interrupts masked cmdr 00 h no commands xbch rbch 00 h C interrupt controlled data transfer (dma disabled) C full-duplex lapb/lapd operation of lap controller C carrier detect auto start of receiver disabled xccr rccr 00 h 1-bit time-slot
semiconductor group 70 sab 82525 sab 82526 saf 82525 saf 82526 7.2 initialization after reset the cpu has to write a minimum set of registers and an optionally set dependent on the required features and operating modes. first, the configuration of the serial port and the clock mode has to be defined via the ccr1 register. the clock mode must be set before power-up, or in the same step with power-up. the cpu may switch the hscx between power-up and power-down mode, which has no influence upon the contents of the registers, i.e. the internal state remains stored. in power-down mode however, all internal clocks and the oscillator circuitry are disabled, no interrupts are forwarded to the cpu. this state can be used as standby mode, when the hscx is temporarily not used, thus lessening the power consumption to a high degree. the individual operating mode must be defined writing the mode register. the need for programming further registers depends on the selected features (clock mode, operating mode, address mode, user demands) according to the following tables: clock mode register 0, 1 C 2, 3, 4, 6, 7 bgr, ccr2 5 ccr2, tsar, tsax, xccr, rccr address mode operating mode 2 byte address field (mode: adm = 1) 1 byte address field (mode: adm = 0) table 8 register setup auto non auto rah1 rah2 ral1 ral2 rah1 set to 00 h rah2 set to 00 h ral1 transparent rah1 rah2 C timr xad1 xad2 rah1 rah2 ral1 ral2 rah1 set to 00 h rah2 ral1 ral2
semiconductor group 71 sab 82525 sab 82526 saf 82525 saf 82526 table 9 user demand registers user demand register cts/rfs interrupt provided ccr2 selective interrupts should be masked mask timer will be used by cpu (external timer mode) timr dma controlled data transfer xbch receive length check feature rlcr extended (module 128) counting rah2 7.3 operational phase after having performed the initialization, the cpu switches each individual channel of the hscx into operational phase by setting the pu bit in the ccr1 register (power-up, if not already done during initialization). initially, the cpu should bring the transmitter and receiver to a defined state by issuing a xres (transmitter reset) and rhr (receiver reset) command via the cmdr register. if data reception should be performed, the receiver must be activated by setting the rac bit in mode to 1. if no "clear to send" function is provided via a modem, the cts pin of the hscx must be connected directly to ground, in order to enable data transmission. now the hscx is ready to transmit and receive data. the control of the data transfer phase is mainly done by commands from cpu to hscx via the cmdr register, and by interrupt indications from hscx to cpu. additional status information, which does not trigger an interrupt, is available in the star register. 7.4 data transmission interrupt mode in transmit direction 2 32 byte fifo buffers (transmit pools) are provided for each channel. after checking the xfifo status by polling the transmit fifo write enable bit (xfw in star register) or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can then be started issuing a xtf or xif command via the cmdr register. if the transmit command does not include an end of message indication (cmdr : xme), the hscx will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt (exir : xdu). the frame may also be aborted per software (cmdr : xres). the data transmission sequence, from the cpus point of view, is outlined in figure 32.
semiconductor group 72 sab 82525 sab 82526 saf 82525 saf 82526 figure 32 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 33. figure 33 interrupt driven transmission sequence example itd00246 xpr interrupt or xfw bit in star register = 1 n command xtf xif / write data (up to 32 bytes) to xfifo end of massage ? command / xtf xif + xme end transmit pool ready ? start n y y serial interface hscx cpu interface itd00247 wr xtf bytes 32 . . . . . . 32 bytes wr command wr bytes 6 . . . xpr xtf + xme xpr xpr xtf transmit 32 32 6 frame (70 bytes)
semiconductor group 73 sab 82525 sab 82526 saf 82525 saf 82526 back to back frames if two or more frames should be transmitted in a high speed sequence without interframe time fill, the transmission sequence according figure 34 has to be used. this means that the closing flag will be immediately followed by an opening flag. the hscx receiver, however, is capable of receiving frames separated by only one (shared) flag. figure 34 continuous frames transmission (flow diagram) itd05883 start transmit pool ready ? y xfifo last frame ? xpr interrupt or xfw bit in star register = 1 : data ? end frame xtf : cmdr ? pool ready transmit y cmdr : xtf end + xme y y cmdr : xme _ < ( 32 bytes)
semiconductor group 74 sab 82525 sab 82526 saf 82525 saf 82526 the activities during frame transmission (supposed two frames, 18 bytes and 52 bytes) is shown in figure 35. figure 35 continuous frames transmission sequence example serial interface hscx cpu interface itd00249 18 wr xtf bytes 18 . . . xme . . . 32 bytes wr xtf wr bytes 20 . . . xtf xpr xtf + xme xpr itf bytes 32 frame 1 bytes frame 2 bytes 20 itf xpr xpr dma mode prior to the data transmission, the length of the next frame to be transmitted must be programmed via the transmit byte count registers (xbch, xbcl). the resulting byte count equals the programmed value plus one byte, i.e. since 12 bits are provided via xbch, xbcl (xbc11. . .xbc0) a frame length of 1 up to 4096 bytes (4 kbytes) can be selected. after this, data transmission can be initiated by command (xtf or xif). the hscx will then autonomously request the correct amount of write bus cycles by activating the drqt line. depending on the programmed frame length, block data transfers of n 32-bytes + remainder (n = 0, 1,128) are requested everytime a 32-byte fifo half (transmit pool) is empty and accessible to the dma controller.
semiconductor group 75 sab 82525 sab 82526 saf 82525 saf 82526 the following figure gives an example of a dma driven transmission sequence with a supposed frame length of 70 bytes, i.e. programmed transmit byte count (xcnt) equal 69 bytes. figure 36 dma driven transmission sequence example wr xcnt wr xtf transmit frame (70 serial interface hscx cpu/dma interface itd00250 (69) drqt(32) wr . . . wr drqt(32) wr wr drqt(6) wr 32 32 6 dma write cycles (70) xpr . . . . . . bytes) 7.5 data reception interrupt mode also 2 32 byte fifo buffers (receive pools) are provided for each channel in receive direction. there are two different interrupt indications concerned with the reception of data: C rpf (receive pool full) interrupt, indicating that a 32 byte block of data can be read from the rfifo and the received message is not yet complete. C rme (receive message end) interrupt, indicating that the reception of one message is completed, i.e. either one message with less than 32 bytes, or the last part of a message with more than 32 bytes is stored in the rfifo. after an interrupt has been processed, i.e. the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing a rmc (receive message complete) command. the cpu has to handle the rpf interrupt before additional 32 bytes are received via the serial interface which would cause a "receive data overflow" condition.
semiconductor group 76 sab 82525 sab 82526 saf 82525 saf 82526 in addition to the message end (rme) interrupt, the following information about the received frame is stored by the hscx in special registers and/or rfifo: table 10 status information after rme interrupt length of message (bytes) rbch, rbcl register address combination and/or rsta rfifo: last byte ral1 rfifo address field rhcr rfifo control field rsta rfifo: last byte type of frame (command/response) rsta rfifo: last byte crc result (good/bad) rsta rfifo: last byte valid frame (yes/no) rsta rfifo: last byte abort sequence recognized (yes/no) rsta rfifo: last byte data overflow
semiconductor group 77 sab 82525 sab 82526 saf 82525 saf 82526 the following figure gives an example of an interrupt controlled reception sequence, supposed that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 37 interrupt driven reception sequence example serial interface hscx cpu interface itd00251 rpf rmc rd 32 32 rd rmc rpf rme rmc rmc rme rme rmc rd status 32 32 2 6 6 receive frame bytes) bytes bytes rd count rd count rd status . . . . . . ... ... ... rd count rd status 1 (66 dma mode if the rfifo contains 32 bytes, the hscx autonomously requests a block data transfer by dma activating the drqr line as long as the start of the 32nd read cycle. this forces the dma controller to continuously perform bus cycles till 32 bytes are transferred from the hscx to the system memory. if the rfifo contains less than 32 bytes (one short frame or the last part of a long frame) the hscx requests a block data transfer depending on the contents of the rfifo according to the following table: rfifo contents (bytes) dma request (bytes) 1, 2, 3 4 - 7 8 - 15 16 - 32 4 8 16 32 note: all available status informations after rme are summarized in table 10.
semiconductor group 78 sab 82525 sab 82526 saf 82525 saf 82526 after the dma controller has been set up for the reception of the next frame, the cpu must be issue a rmc command to acknowledge the completion of the receive frame processing. the hscx will not initiate further dma cycles by activating the drqr line prior to the reception of rmc. note: its also possible to set up the dma controller immediately after the start of a frame has been detected using the hscxs rfs (receive frame start) interrupt option ( see chapter 4.3 ). the following figure gives an example of a dma controlled reception sequence, supposed that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 38 dma driven reception sequence example serial interface hscx cpu/dma interface itd00252 rme 32 32 2 6 rf2 rmc receive frame (66 dma read cycles (68) drqr(8) . . . . . . drqr(8) rd . . . drqr(4) drqr(32) . . . rd rd rd rd . . . drqr(32) rf3 6 rd count 1 bytes) rd rd rme rmc rd rd rd rme rmc rd count rd count
semiconductor group 79 sab 82525 sab 82526 saf 82525 saf 82526 8 detailed register description 8.1 register address arrangement table 11 layout of register addresses abreadwrite refer to page: address register channel 73 74 00 1f : : 40 5f : : rfifo xfifo receive/transmit fifo 75 76 20 60 ista mask interrupt status/mask 79 80 21 61 star cmdr status/comand 82 22 62 mode mode 84 23 63 timr timer 85 85 24 64 exir xad1 extended interrupt/transmit address 1 86 86 25 65 rbcl xad2 receive byte count low/transmit address 2 C87 26 66 C rah1 receive address high 1 87 87 27 67 rsta rah2 receive status/rec. addr. high 2 90 28 68 ral1 receive address low 1 91 90 29 69 rhcr ral2 receive hdlc control/receive addr. low 2 C 92 2a 6a C xbcl transmit byte count low C 92 2b 6b C bgr baudrate generator register 93 2c 6c ccr2 channel configuration register 2 96 95 2d 6d rbch xbch receive/transmit byte count high 96 97 2e 6e vstr rlcr version status/receive frame length check 97 2f 6f ccr1 channel configuration register 1 C 99 30 70 C tsax time-slot assignment transmit C 99 31 71 C tsar time-slot assignment receive C 99 32 72 C xccr transmit channel capacity C 99 33 73 C rccr receive channel capacity note: channel a is not implemented in sab 82526 ral1
semiconductor group 80 sab 82525 sab 82526 saf 82525 saf 82526 8.2 register definitions receive fifo (read) rfifo (00. . .1f/40. . .5f) interrupt controlled data transfer (interrupt mode) selected if dma bit in xbch is reset. up to 32 bytes of receive data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: exactly 32 bytes to be read. rme interrupt: number of bytes to be determined by reading the rbcl, rbch registers. dma controlled data transfer (dma mode) selected if dma bit in xbch if the rfifo contains 32 bytes, the hscx autonomously requests a block data transfer by dma activating the drqr line as long as the start of the 32nd read cycle. this forces the dma controller to continuously perform bus cycles till 32 bytes are transferred from the hscx to the system memory, (level triggered, demand transfer mode of dma controller). if the rfifo contains less than 32 bytes (one short frame or the last of a long frame) the hscx requests a block data transfer depending on the contents of the rfifo according to the following table: rfifo contents (bytes) dma request (bytes) 1, 2, 3 4 - 7 8 - 15 16 - 32 4 8 16 32 additionally an rme interrupt is issued after the last byte has been transferred. as a result, the dma controller may transfer more bytes as actually valid in the current received frame. the valid byte count must therefore be determined by reading the rbch, rbcl registers following the rme interrupt.
semiconductor group 81 sab 82525 sab 82526 saf 82525 saf 82526 transmit fifo (write) xfifo (00. . .1f/40. . .5f) interrupt mode selected if dma bit in xbch is reset. up to 32 bytes of transmit data can be written to the xfifo following an xpr interrupt. dma mode selected if dma bit in xbch is set. prior to any data transfer, the actual byte count of the frame to be transmitted must be written to the xbch, xbcl registers by the user. if data transfer is then initiated via the cmdr register (command xtf or xif), the hscx autonomously requests the correct amount of block data transfers (n 32 + rest, n = 0, 1, ). note: addresses within the address space of the fifos are interpreted equally, i.e. the actual data byte can be accessed with any address within the valid scope.
semiconductor group 82 sab 82525 sab 82526 saf 82525 saf 82526 interrupt status register (read) ista (20/60) rme rpf rsc xpr tin ica exa exb 7 0 value after reset: 00 h rme. . .receive message end one message up to 32 bytes or the last part of a message greater then 32 bytes has been received and is now available in the rfifo. the message is complete! the actual message length can be determined reading the rbch, rbcl registers. additional information is available in the rsta register. rpf. . .receive pool full a block of 32 bytes of a message is stored in the rfifo. the message is not yet completed! note: this interrupt is only generated in interrupt mode! rsc. . .receive status change (significant in auto-mode only!) a status change (receiver ready/receiver not ready) of the opposite station has been detected in auto-mode. (i.e. the hscx has received a rr/rnr supervisory frame according to the hdlc protocol.) the current status can be read from the star register (rrnr bit). xpr. . .transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. tin. . .timer interrupt the internal timer and repeat counter has been expired. ( see also description of timr register! ) ica interrupt of channel a (channel b only) indicates, that an interrupt is caused by channel a and the interrupt source(s) is (are) indicated in the ista register of channel a (i.e. at least one bit of the ista register of channel a is set).
semiconductor group 83 sab 82525 sab 82526 saf 82525 saf 82526 the ica, exa, and exb bit are present in channel b only and point to the ista (cha), exir (cha), and exir (chb) registers. after the hscx has requested an interrupt by turning its int pin to low, the cpu must first read the ista register of channel b and check the state of these bits in order to determine which interrupt source(s) of which channel(s) has caused the interrupt. more than one interrupt source may be indicated by a single interrupt request. after the respective register has been read, exa, and exb are reset. all other bits will be reset after reading ista. to prevent malfunctions, each bit is individually monitored and reset. to generate edges at the int pin it is necessary to mask all interrupts at the end of the interrupt service routine and write back the old mask to the mask register. mask register (write) value after reset: 00 h (all interrupts enabled) each interrupt source can be selectively masked by setting the respective bit in mask (bit positions corresponding to ista register). masked interrupts are not indicated when reading ista. instead, they remain internally stored and will be indicated after the respective mask bit is reset. mask rme rpf rsc xpr tin ica exa exb (20/60) 70 exa extended interrupt of channel a (channel b only) an interrupt is caused by channel b and source(s) is (are) indicated in the exir register of channel b. note: in the event of an extended interrupt, no interrupt request will be generated with a masked exa, exb bit, although this bit is set in ista. note:
semiconductor group 84 sab 82525 sab 82526 saf 82525 saf 82526 extended interrupt register (read) value after reset: 00 h exir xmr xdu exe pce rfo csc rfs 0 0 (24/64) 70 xdu/exe transmit data underrun/extended transmission end the actual frame has been aborted with idle, because the xfifo holds no further data, but the frame is not yet complete! in extended transparent mode, this bit indicates the transmission-end condition. the transmission of the last message has to be repeated because the hscx has received a negative acknowledgement in auto-mode, C or a collision has occurred after sending the 32nd data byte of a message in a bus C configuration. or cts (transmission enable) has been withdrawn after sending the 32nd data byte of a C message in point-to-point configuration. xmr transmit message repeat it is not possible to send transparent-, or i -frames when a xmr or xdu interrupt is indicated. note:
semiconductor group 85 sab 82525 sab 82526 saf 82525 saf 82526 pce protocol error (significant in auto-mode only!) rfo receive frame overflow one frame could not be stored due to occupied rfifo (i.e. whole frame has been lost). this interrupt can be used for statistical purposes and indicates, that the cpu does not respond quickly enough to an incoming rpf, or rme interrupt. csc clear to send status change indicates, that a state transition has occurred at the cts pin. the actual state can be read from star register (cts bit). this interrupt must be enabled setting the cie bit in ccr2. rfs. . .receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after an rfs interrupt, the contents of rhcr ral1 rsta C bit 3-0 are valid and can be read by the cpu. this interrupt must be enabled setting the rie bit in ccr2. the hscx has detected a protocol error, i.e. it has received an s-, or i -frame with incorrect n (r) C an s-frame containing an i -field. C
semiconductor group 86 sab 82525 sab 82526 saf 82525 saf 82526 status register (read) value after reset: 48 h star xdov xfw xrnr rrnr rli cec cts wfa (21/61) 70 xdov transmit data overflow more than 32 bytes have been written to the xfifo. xfw transmit fifo write enable data can be written to the xfifo. xfw is valid if cec = 0 only! note: xrnr transmit rnr (significant in auto-mode only!) indicates the status of the hscx. 0 receiver ready 1 receiver not ready rrnr receive rnr (significant in auto-mode only!) indicates the status of the remote station. 0 receiver ready 1 receiver not ready rli receive line inactive neither flags as interframe time fill nor frames are received via the receive line. significant in point-to-point configurations! note: cec command executing 0 no command is currently executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently executed, no further command can be temporarily written via cmdr register. cec will be active at most 2.5 transmit clock periods. if the hscx is in power down mode cec will stay active. note: cts clear to send state if the cie bit in ccr2 is set, this bit indicates the state of the cts pin. 0 cts is inactive (high signal at cts) 1 cts is active (low signal at cts) wfa waiting for acknowledgement (significant in auto-mode only) indicates the waiting for acknowledgement status of hscx.
semiconductor group 87 sab 82525 sab 82526 saf 82525 saf 82526 command register (write) value after reset: 00 h cmdr (21/61) 70 rmc rhr rnr xrep sti xtf xif xme xres the maximum time between writing to the cmdr register and the execution of the command is 2.5 clock cycles. therefore, if the cpu operates with a very high clock in comparison with the hscxs clock, it's recommended that the cec bit of the star register is checked before writing to the cmdr register to avoid any loss of commands. note: rmc receive message complete confirmation from cpu to hscx, that the actual frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. rhr reset hdlc receiver all data in the rfifo and the hdlc receiver deleted. in dma mode, this command is only issued once after a rme interrupt. the hscx does not generate further dma requests prior to the reception of this command. note: in auto-mode, additionally the transmit and receive sequence number counters are reset. rnr/xrep receiver not ready/transmission repeat the function of this command depends on the selected operation mode (mds1, mds0, adm bit in mode): auto-mode: rnr 0 receiver ready (rr) 1 receiver not ready (rnr) the status of the hscx receiver is set. determines, whether a received frame is acknowledged via an rr, or rnr supervisory frame in auto-mode. extended transparent mode 0, 1 : xrep together with xtf and xme set (write 2 a h to cmdr), the hscx repeatedly transmits the contents of the xfifo (1 32 bytes) without hdlc framing fully transparent, i.e. without flag, crc insertion, bit stuffing. the cyclic transmission is stopped with an xres command!
semiconductor group 88 sab 82525 sab 82526 saf 82525 saf 82526 xtf transmit transparent frame interrupt mode after having written up to 32 bytes the xfifo, this command initiates the transmission of a transparent frame. an opening flag sequence is automatically added to the data by the hscx. dma mode after having written the length of the frame to be transmitted to the xbch, xbcl registers, this command initiates the data transfer from system memory to hscx by dma. serial data transmission starts as soon as 32 bytes are stored in the xfifo. xif transmit i -frame (used in auto-mode only!) initiates the transmission of an i -frame in auto-mode. additional to the opening flag sequence, the address and control field of the frame is automatically added by hscx. xme transmit message end (used in interrupt mode only!) indicates, that the data block written last to the transmit fifo completes the actual frame. the hscx can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. xres transmit reset the contents of the xfifo is deleted and idle is transmitted. this command can be used by the cpu to abort a frame currently in transmission. after setting xres an xpr interrupt is generated in every case. in dma mode, the end of the frame is determined by the transmit byte count in xbch, xbcl! this bit must not be set in dma mode. sti start timer the internal timer is started. note: the timer is stopped by rewriting the timr register after start.
semiconductor group 89 sab 82525 sab 82526 saf 82525 saf 82526 mode register (read/write) value after reset: 00 h mode mds1 mds0 adm tmd rac rts trs tlp (22/62) 70 mds1, mds0 mode select the operating mode of the hdlc controller is selected. 00 auto-mode 01 non-auto mode 10 transparent mode 11 extended transparent mode adm address mode auto-mode, non-auto mode the meaning of this bit varies depending on the selected operating mode: defines the length of the hdlc address field. 0 8-bit address field 1 16-bit address field transparent mode 0 transparent mode 0; no address recognition. 1 transparent mode 1; high byte address recognition. in transparent modes, this bit differentiates between two sub-modes: extended transparent mode; without hdlc framing. 0 extended transparent mode 0; received data in ral1. 1 extended transparent mode 1; received data in rfifo and ral1. in extended transparent modes, the rac bit must set to "0" to enable fully transparent reception! note:
semiconductor group 90 sab 82525 sab 82526 saf 82525 saf 82526 tmd timer mode the operation mode of the internal timer is set. 0 external mode the timer is controlled by the cpu and can be started at any time setting the sti bit in cmdr. 1 internal mode the timer is used internally by the hscx for time-out and retry conditions in auto-mode. (refer to the description of the timr register) rac receiver active switches the receiver to inoperational state. 0 hdlc receiver inactive 1 hdlc receiver active in extended transparent modes this bit must be reset to enable fully transparent reception! rts request to send defines the state and control of rts pin. 0 the rts pin is controlled by the hscx autonomously. rts is activated when a frame transmission starts and deactivated after the transmission operation is completed. 1 the rts pin is controlled by the cpu. if this bit is set, the rts pin is activated immediately and remains active till this bit is reset (not valid in bus configuration). trs timer resolution the resolution of the internal timer (factor k , see description of timr register) is selected 0 k = 32.768 1 k = 512 rxd is disconnected from the mechanical pin and internally connected to txd of the same channel. txd pin remains active. tlp test loop
semiconductor group 91 sab 82525 sab 82526 saf 82525 saf 82526 k is the timer resolution factor which is either 32.768 or 512-clock cycles dependent on the programming of trs bit in mode. tcp is the clock period of transmit data. C C timer register (read/write) timr cnt value (23/63) 75 40 value sets the time period t 1 as follows: t 1 = k (value + 1) tcp where cnt interpreted differently dependent on the selected timer mode (bit tmd in mode). internal timer mode (mode.tmd = 1) retry counter (in hdlc known as n2) cnt indicates the number of s-commands (max. 6) which are transmitted autonomously by the hscx after expiration of time period t 1 , in case an i -frame is not acknowledged by the opposite station. if cnt is set to 7, the number of s-commands is unlimited. external timer mode (mode,tmd = 0) cnt plus value indicates the time period t 2 after which a timer interrupt will be generated. the time period t 2 is t 2 = 32 k cnt tcp + t 1 if cnt is set to 7, a timer interrupt periodically generated after the expiration o f t 1 .
semiconductor group 92 sab 82525 sab 82526 saf 82525 saf 82526 transmit address byte 1 (write) xad1 2-byte address (24/64) 70 xad1 (high byte) 0 (0) 1-byte address xad1 (command) xad1 (and xad2) can be programmed with one individual address byte which is appended automatically to the frame by hscx in auto-mode. the function depends on the selected address mode (bit adm in mode). 2-byte address field (mode.adm = 1) C C xad1 forms the high byte of the 2-byte address field. bit 1 must be set to 0! according to the isdn lapd protocol, bit 1 is interpreted as the c/r (command/response) bit. this is manipulated automatically by the hscx dependent on the setting of the cri bit in rah1: commands transmit responses transmit 1 bit 1 (c/r) 0 cri = 1 0 1 cri = 0 (in the isdn, the high address byte is known as sapi). in accordance with the hdlc protocol, bit 0 should be set to 0, indicating the extension of the address field to two bytes. 1-byte address field (mode.adm = 0) C C according with the x.25 lapb protocol, xad1 indicates a command.
semiconductor group 93 sab 82525 sab 82526 saf 82525 saf 82526 1-byte address xad2 (response) second individually programmable address byte. 2-byte address (mode.adm = 1) C C xad2 builds up the low byte of the 2-byte address field (in the isdn, the low address byte is known as tei) 1-byte address (mode.adm = 0) C C according to the x.25 lapb protocol, xad2 indicates a response, xad1, xad2 registers are used only if the hscx is operated in auto-mode. note: receive byte count low (read) rbcl (25/65) 70 rbc7 rbc0 together with rbch (bits rbc11 C rbc8), the length of the actual received frame (14095 bytes) can be determined. these registers must be read by the cpu following an rme interrupt. transmit address byte 2 (write) xad2 2-byte address (25/65) 70 xad2 (low byte)
semiconductor group 94 sab 82525 sab 82526 saf 82525 saf 82526 rah1 (26/66) 70 rah1 cri 0 in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individual programmable values in rah1, or rah2. rah1 value of the first individual high address byte the setting of the cri bit affects the meaning of the c/r bit in rsta as follows: receive address byte high register 1 (write) cri command/response interpretation (auto-mode and non-auto mode only) commands received responses received c/r meaning 0 c/r value 1 cri = 1 1 0 cri = 0 important: if the 1 byte address field is selected in auto-mode, rah1 must be set to 00 h . rah2 (27/67) 70 rah2 mcs 0 receive address byte high register 2 (write) 10 rah2 value of second individual programmable high address byte. mcs module count select; valid in auto-mode only. 0 basic operation (modulo 8) 1 extended operation (modulo 128) the mcs bit adjusts the control field format according to the hdlc (isdn/lapd). when modulo 128 is selected, in auto-mode the "rhcr" register contains compressed information of the extended control field (see rhcr, register description). rah1, rah2 registers are used in auto and non-auto operating modes when a 2-byte address field has been selected (mode.adm = 1) and in the transparent mode 0. rah2 has to be initialized. note:
semiconductor group 95 sab 82525 sab 82526 saf 82525 saf 82526 receive status register (read) rsta vfr rdo crc rab ha1 ha0 c/r la (27/67) 70 vfr valid frame 1 valid 0 invalid determines whether a valid frame has been received. a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bit), or a frame which is too short depending on the selected operation mode via mode (mds1, mds0, adm) as follows: C C C auto-/non-auto mode (16-bit address): 4 bytes auto-/non-auto mode (8-bit address): 3 bytes transparent mode 1:3 bytes. transparent mode 0:2 bytes. shorter frames are not reported. note: rdo receive data overflow a data overflow has occurred within the actual frame. caution: data loss because the cpu did not serve rme or rpf interrupt in time. crc crc compare/check 0 crc check failed; received frame contains errors. 1 crc check o.k.; received frame is error-free. rab receive message aborted an invalid frame is either the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the cpu.
semiconductor group 96 sab 82525 sab 82526 saf 82525 saf 82526 in operating modes which provide high byte address recognition, the hscx compares the high byte of a 2-bytes address with the contents of two individual programmable registers (rah1, rah2) and the fixed values fe h and fc h (group address). ha1, ha0 high byte address compare; significant only if 2-byte address mode has been selected. dependent on the result of this comparison, the following bit combinations are possible: 10 rah1 has been recognized 00 rah2 has been recognized 01 group address has been recognized if rah1, rah2 contain the identical values, the combination 00 will be omitted. note: c/r command/response; significant only, if 2-byte address mode has been selected. value of the c/r bit (bit of high address byte) in the received frame. the interpretation depends on the setting of the cri bit in the rah1 register. refer also to the description of rah1 register. la low byte address compare; not significant in transparent and extended transparent operating modes. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two programmable registers (ral1, ral2) 0 ral2 has been recognized 1 ral1 has been recognized according to the x.25 lapb protocol, ral1 is interpreted as command and ral2 interpreted as response. rsta corresponds to the last received hdlc frame; it is duplicated into rfifo for every frame (last byte of frame). note:
semiconductor group 97 sab 82525 sab 82526 saf 82525 saf 82526 receive address byte low register 1 (read/write) ral1 (28/68) 70 ral1 auto-/non-auto mode (16-bit address) C write only : ral1 can be programmed with the value of the first individual low address byte. auto-/non-auto mode (8-bit address) C write only : according to x.25 lapb protocol, the address in ral1 is recognized as command address. transparent mode 1 (high byte address recognition) C read only : ral1 contains the byte following the high byte of the address in the receive frame (i.e. the second byte after the opening flag). transparent mode 0 (no address recognition) C read only : ral1 contains the first byte after the opening flag (first byte of received frame). extended transparent modes 0, 1 C read only : ral1 contains the actual data byte currently assembled at the r d pin, by passing the hdlc receiver (fully transparent reception without hdlc framing). C C C C C C the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: receive address byte low register 2 (write) ral2 (29/69) 70 ral2 value of the second individual programmable low address byte. if a one byte address field is selected, ral2 is recognized as response according to x.25 lapb protocol.
semiconductor group 98 sab 82525 sab 82526 saf 82525 saf 82526 receive hdlc control register (read) rhcr (29/69) 70 rhcr value of the hdlc control field corresponds to the last received frame. rhcr is duplicated into rfifo for every frame. note: mode auto-mode,1-byte address (u-frames) (note 1) auto-mode, 2-byte address (u-frames) (note 1) auto-mode, 1-byte address ( i -frames) (note 1) auto-mode, 2-byte address ( i -frames) (note 1) modulo 8 (mcs = 0) control field control field control field control field modulo 128 (mcs = 1) control field (note 2) control field (note 2) control field in compressed form (note 3) control field in compressed form (note 3) contents of rhcr non-auto mode, 1-byte address non-auto mode, 2-byte address transparent mode 1 transparent mode 0 2 nd byte after flag 3 rd byte after flag 3 rd byte after flag 2 nd byte after flag s-frames are handled automatically and are not transferred to the microprocessor. note 1: for i -frames (bit 0 of rhcr = 0) the compressed control field has the same format as in the modulo 8 case, but only the three lsbs of the receive and transmit counters are visible: note 3: for u-frames (bit 0 of rhcr = 1) the control field is as in the modulo 8 case. note 2: n(r) p n(s) 0 bit 76543210
semiconductor group 99 sab 82525 sab 82526 saf 82525 saf 82526 xbcl xbc7 xbc0 (2a/6a) 70 together with xbch (bits xbc11xbc8) this register is used in dma mode only, to program the length (14095 bytes) of the next frame to be transmitted. this allows the hscx to request the correct amount of dma cycles after an xtf or xif command via cmdr. note: the number of transmitted bytes is xbc + 1, e.g. if the content of xbc is 00 exactly one byte will be transmitted. baudrate generator register (write) bgr br7 br0 (2b/6b) 70 together with bits br9, br8 of ccr2, the division factor of the baudrate generator is adjusted. dependent on the programmed value n in br9 C br8 (n = 01023) the division factor k results as follows: br7 C br0baudrate, bit 7 - 0 transmit byte count low (write) k = (n + 1) 2
semiconductor group 100 sab 82525 sab 82526 saf 82525 saf 82526 channel configuration register 2 (read/write) value after reset: 00 h the meaning of the individual bits in ccr2 depends on the selected clock mode via ccr 1 as follows: clock mode 0,1 soc1 soc0 (2c/6c) 0 0 0 cie rie div ccr2 clock mode 2,6 br9 br8 bdf tss tio cie rie div clock mode 3,7 br9 br8 bdf 0 tio cie rie div clock mode 5 soc1 soc0 xcs0 rcs0 tio cie rie div clock mode 4 soc1 soc0 0 0 tio cie rie div in a bus configuration (selected via ccr1) the function of pin rts can be defined 00 rts output is activated during the transmission of a frame. 10 rts output is always high (rts disabled). 11 rts indicates the reception of a data frame (active low). in point-to-point configuration (selected via ccr1) the t d and r d pins may be flipped 0x data is transmitted on t d, received on r d pin (normal case) 1x data is transmitted on r d, received on t d pin soc1, soc0 special output control br9, br8 baudrate, bit 9-8 (higher significant bits, refer to description of bgr register). 0 the division factor of the baudrate generator is set to 1 (constant). 1 the division factor is adjusted with br9 C br0 bits of ccr2 and brg register. bdf baudrate division factor 0 the transmit clock is input to the t clka/t clkb pins. 1 the transmit clock is derived from the baudrate generators output divided by 16. tss transmit clock source select 0 t clka, t clkb pins are inputs 1 t clka, t clkb pins are outputs tio transmit clock input output switch
semiconductor group 101 sab 82525 sab 82526 saf 82525 saf 82526 any state transition at the cts input pin may cause an interrupt which is indicated in the exir register (csc bit). the actual state at the cts pin can be determined reading the cts bit of the star register. 0 disable 1 enable cie clear to send interrupt enable when, the rfs interrupt (via exir) is enabled! rie receive frame start interrupt enable only valid if nrz data encoding is selected. data is transmitted and received inverted. div data inversion together with bits xcs2, xcs1 (rcs2, rcs1) in tsax (tsar) the clock shift relative to the frame synchronization signal of the transmit (receive) time-slot can be adjusted. a clock shift of 0 7 bits is programmable (clock mode 5 only!). xcs0, rcs0 transmit/receive clock shift, bit 0
semiconductor group 102 sab 82525 sab 82526 saf 82525 saf 82526 xbch (2d/6d) 73 dma nrm cas xc xbc11 xbc8 0 transmit byte count high (write) value after reset: 000xxxxx selects the data transfer mode of hscx to system memory. 0 interrupt controlled data transfer (interrupt mode) 1 dma controlled data transfer (dma mode) dma dma mode valid in auto-mode only! use in auto-mode only; reset this bit in non auto-mode, transparent mode, and extended transparent mode. determines the function of the lap controller: 0 full-duplex lapb/lapd operation 1 half-duplex nrm operation nrm normal response mode when set, a high at the cd (a clk) pin enables the respective receiver and data reception is started. cas carrier detect auto start cas has to be "0" for clock mode 1 and 5 note: only valid if dma mode is selected! if the xc bit is set, the hscx continuously requests for transmit data ignoring the transmit byte count programmed via xbch, xbcl. xc transmit continuously valid only if dma mode is selected! together with xbc7 xbc0 the length of the frame to be programmed. xbc11 xbc8 transmit byte count (most significant bits)
semiconductor group 103 sab 82525 sab 82526 saf 82525 saf 82526 rbch (2d/6d) 73 dma nrm cas ov rbc11 rbc8 0 received byte count high (read) value after reset: 000xxxxx dma, nrm, cas these bits represent the read-back value programmed in xbch (see xbch!) more than 4095 bytes received! the received frame exceeded the byte count in rbc11 rbc0. ov counter overflow together with rbcl (bits rbc7 rbc0) the length of the received frame can be determined. rbc11 rbc8 receive byte count (most significant bits) see xbch vstr (2e/6e) 73 cd 0 0 0vn3 vn0 0 version status register (read) this bit represents the inverted state at the cd (a clk) pin even when cas is not enabled. 1 cd active (low) 0 cd inactive (high) cd carrier detect 0:000 version a1 2:010 version a2 4:100 version a3 5:101 version 2.1 vn3 vn0 version number of chip
semiconductor group 104 sab 82525 sab 82526 saf 82525 saf 82526 ccr1 (2f/6f) 7 pu sc1 sc0 ods itf oin cm2 cm1 cm0 0 0 power down (standby) 1 power up (active) pu switches between power up and power down mode 00 nrz data encoding 10 nrzi data encoding 01 bus configuration, timing mode 1 11 bus configuration, timing mode 2 sc1, sc0. . .serial port configuration value after reset: 00 h channel configuration register 1 (read/write) if bus configuration is selected, only nrz coding is supported. note: rlcr (2e/6e) 7 rc rl6 rl0 0 receive length check register (write) 0 receive length check feature disabled 1 receive length check feature enabled rc receive check (on/off) the maximum receive length after which data reception is suspended can be programmed here. depending on the value rl programmed via rl6 rl0, the receive length is (rl + 1) 32 bytes! a frame exceeding this length is treated as if it was aborted by the opposite station (rme interrupt, rab bit set). rl receive length in this case, the receive byte count (rbch, rbcl) is greater than the programmed receive length. all bytes stored in the rfifo are relevant for the receive length check feature including the receiver status byte. note:
semiconductor group 105 sab 82525 sab 82526 saf 82525 saf 82526 defines the function of the transmit data pins (t da, t db) 0. . .t d pins are open drain outputs 1. . .t d pins are push-pull outputs ods output driver select the function of this bit depends on the selected serial port configuration (bit sc0) itf/oin interframe time fill/one insertion point-to-point configurations: itf bus configurations: oin determines the idle (= no data to send) state of the transmit data pins (t da, t db) 0 continuous idle sequences are output (t d pins remain in the "1" state) 1 continuous flag sequences are output ("01111110" bit patterns) in bus configurations, the itf is implicitly set to 0, i.e. continuous "1"s are transmitted, and data encoding is nrz! when this bit is set, a "one" insertion (deletion) mechanism is activated, inserting a "1" after seven consecutive "0"s in the transmit data stream or deleting a "1" in the receive data stream. similar to the hdlcs bit-stuffing mechanism (inserting a "0" after five consecutive "1"s), this method proves to be advantageous when the receive clock is recovered from the receive data stream by means of dpll, because it is guaranteed that at least after seven bits a transition occurs in the receive data in case of long "0" sequences! cm2, cm1, cmo clock mode selects one of the 8 different clock modes 000 clock mode 0 .. .. .. 111 clock mode 7 since in time-slot oriented systems the t d pin is not tristated automatically out of the programmed time-slot, the t d pin should be configured as open drain in time-slot oriented bus systems. note:
semiconductor group 106 sab 82525 sab 82526 saf 82525 saf 82526 tsax (30/70) 7 tsnx xcs2 xcs1 this registers is only used in clock mode 5! time-slot assignment register transmit (write) 210 selects one of up 64 possible time-slots (00 h C 3 f h ) in which data is transmitted. the number of bits per time-slot can be programmed via xccr. tsnx time-slot number transmit together with the xcs0 in ccr2, the transmit clock shift can be adjusted. xcs2, xcs1 transmit clock shift, bit 2-1 this register is only used in clock mode 5! time-slot assignment register receive (write) tsar (31/71) 7 tsnr rcs2 rcs1 0 defines one of up to 64 possible time-slots (00 h C 3 f h ) in which data is received. the number of bits per time-slot can be programmed via rccr. tsnr time-slot number receive together with bit rcs0 in ccr2, the receive clock shift can be adjusted. rcs2, rcs1 receive clock shift, bit 2-1
semiconductor group 107 sab 82525 sab 82526 saf 82525 saf 82526 value after reset: 00 h this register is only used in clock mode 5. transmit channel capacity register (write) xccr (32/72) 7 xbc7 xbc0 0 defines the number of bits to be transmitted with a time-slot: number of bits = xbc + 1. (1 256 bits/time-slot) xbc7 xbc0 transmit bit count, bit 7-0 receive channel capacity register (write) rccr (33/73) 7 rbc7 rbc0 0 value after reset: 00 h this register is only used in clock mode 5. defines the number of bits to be received within a time-slot: number of bits = rbc + 1. (1 256 bits/time-slot) rbc7 rbc0 receive bit count, bit 7-0
semiconductor group 108 sab 82525 sab 82526 saf 82525 saf 82526 sab 82525 sab 82526 saf 82525 saf 82526 absolute maximum ratings 9 electrical characteristics symbol t a t a t stg v s v max parameter ambient temperature under bias: sab saf storage temperature voltage on any pin with respect to ground maximum voltage on any pin limit values 0 to 70 C 40 to 85 C 65 to 125 C 0.4 to v dd + 0.4 6 unit c c c v v note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. characteristics sab: t a = 0 to 70 c; v dd = 5 v 5 %; v ss = 0 v saf: t a = C 40 to 85 c; v dd = 5 v 5 %; v ss = 0 v parameter symbol min. unit condition limit values l-input voltage v il C 0.4 v h-input voltage v ih 2.0 v max. 0.8 v cc + 0.4 l-output voltage v ol v v i ol = 7 ma (pins t d, r d) i ol = 2 ma (all other) 0.45 h-output voltage h-output voltage v oh v oh 2.4 v dd C 0.5 v v i oh = C 400 m a i oh = C 100 m a power supply current operational power down 8 1.5 ma ma v dd = 5 v, c p = 4 mhz inputs at 0 v/ v dd , no output loads input leakage current output leakage current i li i lo m a 0 v < v in < v dd to 0 v 0 v < v out < v dd to 0 v 10 i cc i cc
semiconductor group 109 sab 82525 sab 82526 saf 82525 saf 82526 capacitances t a = 25 c; v dd = 5 v 5 %; v ss = 0 v, f c = 1 mhz, unmeasured pins returned to gnd. characteristics sab: t a = 0 to 70 c; v dd = 5 v 5 % saf: t a = C 40 to 85 c; v dd = 5 v 5 % inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and at 0.8 v for a logical "0". the ac testing input/output waveforms are shown below. input/output waveform for ac tests parameter symbol typ. unit limit values input capacitance f c = 1 mhz c in 5pf output capacitance c out 8pf max. 10 15 i /o c i/o 10 pf 20 its02702 = load c test under device 0.45/0.4 2.4/2.4 2.0 0.8 0.8 2.0 test points pf 150
semiconductor group 110 sab 82525 sab 82526 saf 82525 saf 82526 microcontroller interface timing intel bus mode m p read cycle m p write cycle multiplexed address timing cs x rd d0 - d7 t rd data t df rr tt ri itt00953 drh t drqr cs x wr d0 - d7 t dw data t wd ww tt wi drh t drqt itt00954 cs x wr a0 - a6 t la cs x rd ale t als t al t aa itt00955
semiconductor group 111 sab 82525 sab 82526 saf 82525 saf 82526 microcontroller interface timing intel bus mode address timing cs x wr a0 - a6 t dcd dack cs x rd itt00956
semiconductor group 112 sab 82525 sab 82526 saf 82525 saf 82526 motorola bus mode m p read cycle m p write cycle address timing cs x ds d0 - d7 t rd data t df dsd t rr tt ri r/w t drh drqr itt00957 t rwh cs x ds d0 - d7 t dw data t wd dsd t ww tt wi r/w drh t drqt itt00958 rwh t a0 - a6 t ah t as dack cs x ds itt00959
semiconductor group 113 sab 82525 sab 82526 saf 82525 saf 82526 parameter symbol min. unit limit values address setup time to ale t al 10 ns max. address hold time from ale t la 10 ns ale pulse width t aa 25 ns address latch setup time to wr , rd t als 0ns address setup time to wr , rd t as 10 ns address hold time from wr , rd t ah 10 ns dma request delay: sab saf t drh ns ns 80 90 rd pulse width t rr ns data output delay from rd t rd ns 60 data float delay from rd t df ns 25 rd control interval t ri ns wr pulse width t ww ns data setup time to wr x cs /ds x cs t dw ns data hold time from wr x cs /ds x cs t wd ns wr control interval t wi ns t dsd ns interface timing t rdh ns t cds ns t rds ns t cdh ns t xdd2 ns t rtd1 ns serial interface timing receive data hold collision data setup receive data setup collision data hold transmit data delay, falling clock edge request to send delay 1 5 5 20 30 20 68 10 120 60 10 35 10 60 0 70 t cp ns t cpl ns t rtd2 ns t cph ns clock period clock period low request to send delay 2 clock period high 240 90 10 85 90 80 90 70 25 sab saf 75 120 85 rd delay after wr set up t xdd1 ns transmit data delay, rising clock edge 10 68 75
semiconductor group 114 sab 82525 sab 82526 saf 82525 saf 82526 serial interface timing t rds t rdh t cpl t cp t cph t xdd t cds t cdh t xdd t rtd t rtd t rtd bus timing bus timing r rtsa/b mode 2 mode 2 cph t cp t cpl t mode 1 timing bus rtd t rtd t clock rxda/b clock x txda/b txda/b cxda/b ctsa/b rtsa/b rtsa/b 1 2 2 2 1 itt00960 1 2
semiconductor group 115 sab 82525 sab 82526 saf 82525 saf 82526 strobe timing (clock mode1) itt00961 t xdd t xsz t xcz t xdd t sdd t xsh t xss bus timing mode 2 rxclk txclk txd txd t xcz axclk rsd t t xsd rsh t rss t symbol unit limit values t rss ns t rsh ns t rsd ns t xsd ns t xss ns t xsh ns parameter receive strobe setup receive strobe hold receive strobe delay transmit strobe delay transmit strobe setup transmit strobe hold 60 30 30 30 60 30 min. max. t sdd ns t xcz ns t xdd ns t xsz ns strobe data delay high impedance from clock transmit data delay high impedance from strobe 90 50 68 50
semiconductor group 116 sab 82525 sab 82526 saf 82525 saf 82526 clock mode 5 synchronization timing itt00962 t sd t ss t sw t tcd t tcd t tcd t tcd rxclk axclk txclk txclk bus timing mode 2 symbol unit limit values t ss ns t sw ns t sd ns t tcd ns parameter sync pulse setup sync pulse width sync pulse delay time-slot control delay 30 40 30 10 75 min. max.
semiconductor group 117 sab 82525 sab 82526 saf 82525 saf 82526 symbol unit limit values f clk mhz f clk mhz parameter clock frequency baudrate generator not used clock frequency baudrate generator used 19.3 12.3 min. max. clock mode 2, 3, 6, 7 internal clocking symbol unit limit values t rwh ns parameter res high 1800 min. max. reset timing res characteristics cd timing itt05882 60 ns >>ns 30 rxclk rxd axclk (cd)
semiconductor group 118 sab 82525 sab 82526 saf 82525 saf 82526 10 quartz specifications characterization of quartz crystals for the hscx C mode of oscillation parallel resonance C frequency calibration tolerance 50 ppm C frequency shift during lifetime 10 ppm C temperature coefficient/frequency drift 50 ppm within the temperature range C motional capacitance 15 ff 20% C effective serial resistance 50 w for 19.2 mhz C shunt capacitance 7 pf C drive level 1 mw C recommended type hc - 49/u (ansi - standard)
semiconductor group 119 sab 82525 sab 82526 saf 82525 saf 82526 upgrades of hscx version a3 the hscx version a3 is fully upward compatible to version a2. the differences with respect to hscx technical manual rev. 2.89 are shown in table 12 . table 12 differences hscx a2 C hscx a3 differences ver. a2 ver. a3 user manual chapter t ri, t wi 70 ns 9 t aa 50 ns 9 t la 20 ns 9 t drh 85 ns 9 t rd 120 ns 9 t rds 5 ns 9 t rdh 30 ns 9 t xdd 70 ns 9 iol value, pin t d 2 ma 9 vstr value 02h 8 60 ns 25 ns 10 ns 80 ns 100 ns; saf110 ns 20 ns 5 ns 68 ns 7 ma 04h the following additional features are implemented in hscx a3. transmission in back to back frames. two or more frames may be transmitted continously without interframe time fill t d, r d flip in clock modes 0, 1, 4 and 5 pins r d and t d may be flipped (refer to ccr2 register soc0 and soc1 bit) status register in auto-mode, start: bit 0 indicates the waiting for acknowledgement status t cds 0 ns 9 5 ns t ah 20 ns 9 10 ns t dw 30 ns 9 10 ns appendix a
semiconductor group 120 sab 82525 sab 82526 saf 82525 saf 82526 upgrades of hscx version v2.1 3 version id the bits vn3 vn0 of the version status register (vstr) contain the value 5 for version v2.1. all hscx version numbers are listed below: 4 rnr flow control in auto-mode no more timing restrictions exist for hscx v2.1 when the cpu accesses the rnr-bit of the command register (cmdr). 5 i -frames with p = 0 in nrm auto-mode in multipoint configurations using the hdlc normal response mode (nrm) the p-bit of the control field carries out the polling function. the primary station normally polls the other secondary stations by transmitting either rr frames with p = 1 or i -frames with p = 1. i -frames with p = 0 may be used by the primary station to transmit data to an individual secondary station without requesting data from this station at the same time. in this case the secondary station will receive and acknowledge this i -frame, but will not react by transmitting any data to the primary station. in the following it is assumed that the secondary station is waiting for transmission. a secondary station using an hscx va3 in nrm auto-mode will transmit data to the primary station after it has received an i -frame with of p = 0 or = 1. the new hscx v2.1 handles the p-bit of i -frames according to iso 4335. it will transmit data to the primary station after it has received an i -frame with p = 1, but not after an i -frame has been received with p = 0. 6 transmission of back-to-back frames the new hscx v2.1 supports back-to-back frame transmission in all clock modes without any problem, including the strobe modes (clock mode 1 and 5). 7int output signal the int output signal of the hscx v2.1 does not change its value during a write access to the hscx (cs x wr for intel and ds x wr for motorola). vn3 0 version 0: 000 va1 2: 010 va2 4: 100 va3 5: 101 v2.1
semiconductor group 121 sab 82525 sab 82526 saf 82525 saf 82526 8 clock recovery (dpll) in case the dpll detects an edge in the data stream in the range of dpll count 5 to 10 (phase shift) and this is the only one in the assumed bit cell period, then the dpll receive clock phase is shifted by a certain dpll count value. the dpll value and its corresponding phase shift in degree is listed below for the hscx versions va3 and v2.1: hscx version dpll count phase shift va3 8 180 v2.1 7 157.5 differences ver. a3 ver. 2.1 t rd t rr t ri t xdd1 min t rtd1 min t rtd2 min t tcd min 100/110 ns 120 ns 60 ns 20 ns 30 ns 20 ns 20 ns 60/70 ns 70 ns 35 ns 10 ns 10 ns 10 ns 10 ns
semiconductor group 122 sab 82525 sab 82526 saf 82525 saf 82526 hscx auto-mode: specific points appendix b hscx auto-mode of sab 82525/sab 82520 (hscx/hscc) is optimized for a window size of one. therefore the following simplifications are made: no rej-frame is generated, an rr-frame will be transmitted instead. if a rej-frame is received it will be handled like an rr-frame. the transmit/receive variables n(r)/n(s) are checked within the window size (i.e. one), only the lsb is evaluated. an i -frame with an incorrect n(r)-value is not accepted, an error interrupt (exir:pce) is generated. the timer recovery state is cancelled if a positive acknowledgement (updated n(r)) is received. selective reject is treated like rr. after sending an i -frame the hscx cannot transmit any frame before an acknowledgement or an xres-command. two byte addresses: an i -frame with c = 0 is accepted without error indication.
semiconductor group 123 sab 82525 sab 82526 saf 82525 saf 82526 appendix c application example hscx with 80(c)188 using dma dma information, see chapter 4. appendix d hscx for siemens primary access interface the siemens devices for the primary access interface are the advanced cmos frame aligner (acfa) and the primary access transceiver (pract). these devices can directly be connected to the hscx without any additional glue logic. in combination with the hscx this application is the most effective way to build a powerful and flexible primary access interface, especially supporting different combined b channel paths over long distances (lan-wan internetworking). the following block diagram illustrates how easy it is to integrate the hscx into a primary access application based on siemens devices. hscx system integration for primary rate interface t1/e1 siemens system interface (acfa/pract) its05880 txda rxda rxclka axclka txdb rxdb rxclkb axclkb hscx sab 82525 v cc xdi rdo xrclk xdop xdom rdip rdim rrclk xtop xtom sypq sclk acfa peb 2035 dual rail interface clk4m fsc clk2m fsc pract 22320 peb
semiconductor group 124 sab 82525 sab 82526 saf 82525 saf 82526 the adaption of the axclka/b pulses is solved by means of shifting the receive data and transmit data in the acfa device appropriately. in this case the axclka and axclkb synchronization pulses are also identical. the acfa device contains special registers to control the bit shift of the serial bit streams at the system interface (see acfa data sheet). with the following register programming the bit shift selected is t = C 510 for the hscx transmit data and t = 1 for the receive data respectively. the programming is as follows: xdi: xc1.xto = 3d h => x = 494 => t = C 510 xc0.xco = 07 h rdo: rc1.rto = 00 h => x = 3 => t = 1 rc0. rco = 03 h the timing in principle is depicted in the following diagram. without all details of a typical electrical timing it illustrates how the different signals from hscx, acfa and pract are mapped in such a primary access system. hscx signal mapping for primary rate interface t1/e1 siemens system interface (acfa/pract) itd05881 clk4m fsc axclka/b rxclka/b txclka/b txda/b = rxda/b = = = = xdi rdo fsc clk2m (t (t = = -510) 1) = : channel 0, bit 0 (least significant bit) acfa programming for appropriate delays (see acfa data sheet): xdi : rdo : t = - 510 = > x = 495 = > xc1.xto = 3d xc0.xco = 7 3 = rc0.rco 0 = rc1.rto > = 3 = x > = 1 = t , h h h ,
semiconductor group 125 sab 82525 sab 82526 saf 82525 saf 82526 11 package outlines gpl05102 plastic package, p-lcc-44-1 (smd) (plastic-leaded chip carrier) smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm
semiconductor group 126 sab 82525 sab 82526 saf 82525 saf 82526 plastic package, p-mqfp-44-2 (smd) (plastic-leaded chip carrier) gpm 05622 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm

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